🧠 Single Neuron Hardware Accelerator Engine - VLSI + FPGA Projects

🏆 1st Place Winner — VLSI SPEAR Project, Faculty of Engineering Final Projects Competition, Tel Aviv University

This repository serves as a landing page for a two-team collaborative academic project, developed as part of the Electrical Engineering capstone course at Tel Aviv University.

The project includes both a custom silicon chip (ASIC) implementation of a perceptron neuron and a real-time FPGA-based test environment.

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📂 Repository Structure

The repository is organized into two branches — each maintained independently by a dedicated team:

Branch	Description
main.rtl_block_design	RTL-to-GDSII chip design. Includes RTL code, synthesis & physical design scripts, verification tests, and full signoff reports. This team won 1st place in the final project competition.
FPGA	FPGA testbench and validation environment using the DE10-Lite board. Includes randomized vector generation and simulation setup.

ℹ️ The main branch is only a navigation landing page. Please follow the appropriate branch for code, documentation, and usage instructions.

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🎓 Academic Context

• Developed as part of the final project at Tel Aviv University.
• The chip team (RTL to GDSII) won first place in the 2025 Final Project Competition at the Faculty of Engineering.

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🔗 Quick Links

• CHIP Branch — RTL to GDSII
• FPGA Branch — Board Validation Environment