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CPU_verilog

In class(CECS301 @CSULB) lab assignment for creating 16-bit CPU

The main source files are .v files

The content will be
(1) Universal_Shift_Register
(2) Sequence_detector
(3) Sequence_detector_on_Hex (on 7-segment display)
(4) Memory_and_Display_Controller
(5) Register_Files
(6) Integer_Data_Path
(7) CPU_Execution_Unit
(8) 16bit_RISC_Processor

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In class(CECS301 @CSULB) lab assignment for creating 16-bit CPU

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