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| 1 | +# Introduction to Intel Top Swap A/B Redundancy for coreboot |
| 2 | + |
| 3 | +The problem addressed by this functionality is that when a |
| 4 | +platform's firmware crashes during the boot process, the only mode |
| 5 | +of recovery is usually taking apart the platform, attaching an |
| 6 | +SPI clip and flashing recovery firmware as per our recovery guides |
| 7 | +([example](https://docs.dasharo.com/unified/protectli/recovery/)). |
| 8 | + |
| 9 | +With the Top Swap A/B redundancy, there are two firmware slots - **A** and |
| 10 | +**B**, of which **A** is a read-only golden copy, and **B** is the update |
| 11 | +partition. A firmware update is going to target the **B** slot, and boot from |
| 12 | +it. Should the new firmware fail, the platform can be brought back to life by |
| 13 | +performing a **CMOS reset**, which will cause the platform to boot from the safe |
| 14 | +slot **A** again. |
| 15 | + |
| 16 | +This should significantly reduce the friction of testing the firmware, |
| 17 | +especially during development and at early beta stages. |
| 18 | + |
| 19 | +## How It Works |
| 20 | + |
| 21 | +* **Top Swap Control**: The Intel Top Swap feature allows the PCH to take two |
| 22 | +physically topmost chunks of the BIOS flash chip, and decide in which order |
| 23 | +to map them - effectively allowing to swap the two chunks. |
| 24 | + |
| 25 | +* **A/B Slot Setup**: The top of the firmware is divided into two slots: |
| 26 | +`BOOTBLOCK` and `TOPSWAP`, which contain bootblocks "chosen" by the Top |
| 27 | +Swap mechanism. They in turn choose `COREBOOT` and `COREBOOT_TS` regions |
| 28 | +respectively to load consecutive stages from. |
| 29 | + |
| 30 | +* **Runtime CMOS Control**: The CMOS option `attempt_slot_b` controls the Top |
| 31 | +Swap state, also enabling users to manually select the active slot by setting |
| 32 | +this value via nvramtool. If the option is set, the platform will attempt |
| 33 | +booting slot **B**. |
| 34 | + |
| 35 | +## Updating Firmware with Flashrom |
| 36 | + |
| 37 | +If you wish to update the firmware using Flashrom, you need to follow |
| 38 | +these additional steps: |
| 39 | + |
| 40 | +```bash |
| 41 | +sudo flashrom -p internal -w coreboot.rom --fmap -i TOPSWAP -i COREBOOT_TS --noverify-all |
| 42 | +sudo nvramtool -w attempt_slot_b=Enable |
| 43 | +``` |
| 44 | + |
| 45 | +This command sequence writes the new firmware image into the appropriate regions |
| 46 | +(`TOPSWAP` and `COREBOOT_TS`) and enables the Top Swap feature by setting the |
| 47 | +`attempt_slot_b` CMOS option to "Enable". This ensures that after the next |
| 48 | +reboot, the system will boot from the newly updated slot. |
| 49 | + |
| 50 | +## Further reading |
| 51 | + |
| 52 | +For a more detailed documentation of the implementation, please read the |
| 53 | +[upstream coreboot documentation](https://doc.coreboot.org/soc/intel) |
| 54 | +(_"doc.coreboot.org/soc/intel/redundancy.html"_, not yet available as of |
| 55 | +February 25th 2026, can also be viewed |
| 56 | +[here](https://github.com/coreboot/coreboot/blob/main/Documentation/soc/intel/redundancy.md)). |
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