RISC-V Processor

This Repo is my final project for Digital System Design Lab that describe a 5 stage pipelined processor running the RV32I implementation written in Verilog.

RISC-V reference

• Textbook: Digital Design and Computer Architecture: RISC-V Edition by Sarah L. Harris and David Harris
• RISC-V Reference Manual.

FPGA Board

This project will implement on the Altera Board.

What's Next?

This project serves as the foundation for a complete, FPGA-based embedded systems with RISC-V SoC, Planned features include:

• Connecting components through standard bus interfaces such as UARTX and SPI.
• Implementing RTOS.

This updating RISC-V project will be released publicly during the summer of this year.