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Add source code for v1.1.1 release
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‎source/backend/api_info.cpp

+1-1
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@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief Implementation for the API Info class.

‎source/backend/api_info.h

+1-1
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11
//=============================================================================
2-
// Copyright (c) 2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief Definition for the API Info class.

‎source/backend/asic_info.cpp

+1-1
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@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief Implementation for the ASIC Info class.

‎source/backend/asic_info.h

+1-1
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@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief Definition for the ASIC Info class.

‎source/backend/bvh/bvh_bundle.cpp

+1-1
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@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2021-2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief BVH bundle implementation.

‎source/backend/bvh/bvh_bundle.h

+1-1
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@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2021-2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief BVH bundle definition.

‎source/backend/bvh/bvh_index_reference_map.cpp

+1-1
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@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2021-2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief BVH Index reference map implementation.

‎source/backend/bvh/bvh_index_reference_map.h

+1-1
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@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2021-2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief BVH Index reference map definition.

‎source/backend/bvh/dxr_definitions.h

+4-3
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2021-2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief Definition of the DXR helper functions and definitions.
@@ -66,7 +66,7 @@ namespace dxr
6666
// See https://microsoft.github.io/DirectX-Specs/d3d/Raytracing.html#d3d12_raytracing_instance_flags
6767
enum class InstanceFlags : std::uint32_t
6868
{
69-
kFlagNone = 0,
69+
kFlagNone = 0,
7070
kFlagTriangleCullDisable = 0x1,
7171
kFlagTriangleCCW = 0x2,
7272
kFlagForceOpaque = 0x4,
@@ -81,7 +81,7 @@ namespace dxr
8181

8282
enum class VertexBufferFormat : std::uint32_t
8383
{
84-
kFormatUnknown = 0,
84+
kFormatUnknown = 0,
8585
};
8686

8787
// Description of geometry: vertex and index buffer for meshes,
@@ -170,6 +170,7 @@ namespace dxr
170170

171171
// Byte sizes for all structs contained in BVH4 dumps on RT IP 1.1.
172172
constexpr std::uint32_t kInvalidNode = UINT32_MAX;
173+
constexpr std::uint32_t kFusedInstanceNodeSize = 256;
173174
constexpr std::uint32_t kInstanceNodeSize = 128;
174175
constexpr std::uint32_t kFp32BoxNodeSize = 128;
175176
constexpr std::uint32_t kFp16BoxNodeSize = 64;

‎source/backend/bvh/encoded_rt_ip_11_bottom_level_bvh.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2021-2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief RT IP 1.1 (Navi2x) specific bottom level acceleration structure

‎source/backend/bvh/encoded_rt_ip_11_bottom_level_bvh.h

+1-2
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@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2021-2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief RT IP 1.1 (Navi2x) specific bottom level acceleration structure
@@ -116,7 +116,6 @@ namespace rta
116116

117117
std::vector<std::uint8_t> leaf_nodes_ = {}; ///< Leaf nodes (triangle, procedural).
118118
std::vector<dxr::amd::GeometryInfo> geom_infos_ = {}; ///< Array of geometry info.
119-
std::vector<dxr::amd::NodePointer> primitive_node_ptrs_ = {}; ///< Pointer to the leaf nodes.
120119
std::vector<std::uint8_t> sideband_data_ = {}; ///< Sideband data for compression.
121120
std::vector<float> triangle_surface_area_heuristic_ = {}; ///< Surface area heuristic values for the triangles.
122121
float surface_area_heuristic_ = 0.0f; ///< The precalculated Surface area heuristic for this BLAS.

‎source/backend/bvh/encoded_rt_ip_11_top_level_bvh.cpp

+80-46
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2021-2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief RT IP 1.1 (Navi2x) specific top level acceleration structure
@@ -25,9 +25,45 @@ namespace rta
2525
{
2626
}
2727

28-
const std::vector<dxr::amd::InstanceNode>& EncodedRtIp11TopLevelBvh::GetInstanceNodes() const
28+
std::int32_t EncodedRtIp11TopLevelBvh::GetInstanceNodeSize() const
2929
{
30-
return instance_nodes_;
30+
if (GetHeader().GetPostBuildInfo().GetFusedInstances() == true)
31+
{
32+
return dxr::amd::kFusedInstanceNodeSize;
33+
}
34+
else
35+
{
36+
return dxr::amd::kInstanceNodeSize;
37+
}
38+
}
39+
40+
const dxr::amd::InstanceNode* EncodedRtIp11TopLevelBvh::GetInstanceNode(const dxr::amd::NodePointer* node_ptr) const
41+
{
42+
const auto& header_offsets = GetHeader().GetBufferOffsets();
43+
uint32_t byte_offset = node_ptr->GetByteOffset();
44+
byte_offset -= header_offsets.leaf_nodes;
45+
46+
if (byte_offset >= instance_node_data_.size())
47+
{
48+
return nullptr;
49+
}
50+
51+
return reinterpret_cast<const dxr::amd::InstanceNode*>(&instance_node_data_[byte_offset]);
52+
}
53+
54+
int32_t EncodedRtIp11TopLevelBvh::GetInstanceIndex(const dxr::amd::NodePointer* node_ptr) const
55+
{
56+
const auto& header_offsets = GetHeader().GetBufferOffsets();
57+
uint32_t byte_offset = node_ptr->GetByteOffset();
58+
byte_offset -= header_offsets.leaf_nodes;
59+
60+
if (byte_offset >= instance_node_data_.size())
61+
{
62+
return -1;
63+
}
64+
65+
uint32_t instance_node_size = GetInstanceNodeSize();
66+
return byte_offset / instance_node_size;
3167
}
3268

3369
bool EncodedRtIp11TopLevelBvh::HasBvhReferences() const
@@ -93,11 +129,12 @@ namespace rta
93129
auto rt_ip11_header = CreateRtIp11AccelerationStructureHeader();
94130
rt_ip11_header->LoadFromBuffer(dxr::amd::kAccelerationStructureHeaderSize, buffer.data() + chunk_header.header_offset);
95131

96-
instance_nodes_ = std::vector<dxr::amd::InstanceNode>(rt_ip11_header->GetPrimitiveCount());
97-
buffer_stream.Read(dxr::amd::kInstanceNodeSize * instance_nodes_.size(), instance_nodes_.data());
132+
int32_t num_instance_nodes = rt_ip11_header->GetPrimitiveCount();
133+
instance_node_data_.resize(num_instance_nodes * GetInstanceNodeSize());
134+
buffer_stream.Read(instance_node_data_.size(), instance_node_data_.data());
98135

99-
const auto prim_node_ptr_size = instance_nodes_.size() * sizeof(dxr::amd::NodePointer);
100-
primitive_node_ptrs_.resize(instance_nodes_.size());
136+
const auto prim_node_ptr_size = num_instance_nodes * sizeof(dxr::amd::NodePointer);
137+
primitive_node_ptrs_.resize(prim_node_ptr_size);
101138
buffer_stream.Read(prim_node_ptr_size, primitive_node_ptrs_.data());
102139

103140
buffer_stream.Close();
@@ -109,7 +146,7 @@ namespace rta
109146
{
110147
bool result = BuildInstanceList();
111148
ScanTreeDepth();
112-
instance_surface_area_heuristic_.resize(instance_nodes_.size(), 0);
149+
instance_surface_area_heuristic_.resize(header_->GetPrimitiveCount(), 0);
113150
return result;
114151
}
115152

@@ -124,29 +161,31 @@ namespace rta
124161
else
125162
{
126163
// Fix up the instance node addresses.
127-
for (auto& instance_node : instance_nodes_)
164+
int32_t byte_offset = 0;
165+
while (byte_offset < instance_node_data_.size())
128166
{
129-
if (instance_node.IsInactive())
167+
dxr::amd::InstanceNode* instance_node = reinterpret_cast<dxr::amd::InstanceNode*>(&instance_node_data_[byte_offset]);
168+
if (!instance_node->IsInactive())
130169
{
131-
continue;
132-
}
170+
uint64_t address = instance_node->GetDesc().GetBottomLevelBvhGpuVa(dxr::InstanceDescType::kRaw);
171+
uint32_t meta_data_size = instance_node->GetExtraData().GetBottomLevelBvhMetaDataSize();
172+
const GpuVirtualAddress old_reference = address - meta_data_size;
133173

134-
uint64_t address = instance_node.GetDesc().GetBottomLevelBvhGpuVa(dxr::InstanceDescType::kRaw);
135-
uint32_t meta_data_size = instance_node.GetExtraData().GetBottomLevelBvhMetaDataSize();
136-
const GpuVirtualAddress old_reference = address - meta_data_size;
137-
138-
const auto it = reference_map.find(old_reference);
139-
if (it != reference_map.end())
140-
{
141-
const auto new_relative_reference = it->second;
142-
instance_node.GetDesc().SetBottomLevelBvhGpuVa(new_relative_reference << 3, dxr::InstanceDescType::kRaw);
143-
}
144-
else
145-
{
146-
missing_set.insert(old_reference);
147-
const auto new_relative_reference = 0;
148-
instance_node.GetDesc().SetBottomLevelBvhGpuVa(new_relative_reference << 3, dxr::InstanceDescType::kRaw);
174+
const auto it = reference_map.find(old_reference);
175+
if (it != reference_map.end())
176+
{
177+
const auto new_relative_reference = it->second;
178+
instance_node->GetDesc().SetBottomLevelBvhGpuVa(new_relative_reference << 3, dxr::InstanceDescType::kRaw);
179+
}
180+
else
181+
{
182+
missing_set.insert(old_reference);
183+
const auto new_relative_reference = 0;
184+
instance_node->GetDesc().SetBottomLevelBvhGpuVa(new_relative_reference << 3, dxr::InstanceDescType::kRaw);
185+
}
149186
}
187+
188+
byte_offset += GetInstanceNodeSize();
150189
}
151190
}
152191
}
@@ -184,18 +223,13 @@ namespace rta
184223
if (node_ptr.IsInstanceNode())
185224
{
186225
auto byte_offset = node_ptr.GetByteOffset() - header_offsets.leaf_nodes;
187-
188-
uint32_t instance_node_size = sizeof(dxr::amd::InstanceNode);
189-
uint32_t instance_index = byte_offset / instance_node_size;
190-
191-
const auto& instance_nodes = GetInstanceNodes();
192-
if (instance_index < instance_nodes.size())
226+
if (byte_offset < instance_node_data_.size())
193227
{
194-
const dxr::amd::InstanceNode* instance_node = &instance_nodes[instance_index];
195-
const auto& desc = instance_node->GetDesc();
228+
const dxr::amd::InstanceNode* instance_node = reinterpret_cast<const dxr::amd::InstanceNode*>(&instance_node_data_[byte_offset]);
196229

230+
const auto& desc = instance_node->GetDesc();
197231
uint64_t blas_index = desc.GetBottomLevelBvhGpuVa(dxr::InstanceDescType::kRaw) >> 3;
198-
uint32_t address = (instance_index * sizeof(dxr::amd::InstanceNode)) + header_offsets.leaf_nodes;
232+
uint32_t address = byte_offset + header_offsets.leaf_nodes;
199233
dxr::amd::NodePointer new_node = dxr::amd::NodePointer(dxr::amd::NodeType::kAmdNodeInstance, address);
200234

201235
if (instance_list_.find(blas_index) == instance_list_.end())
@@ -259,12 +293,16 @@ namespace rta
259293
uint64_t EncodedRtIp11TopLevelBvh::GetInactiveInstanceCountImpl() const
260294
{
261295
uint64_t inactive_count{0};
262-
for (auto& instance_node : instance_nodes_)
296+
int32_t byte_offset = 0;
297+
while (byte_offset < instance_node_data_.size())
263298
{
264-
if (instance_node.IsInactive())
299+
const dxr::amd::InstanceNode* instance_node = reinterpret_cast<const dxr::amd::InstanceNode*>(&instance_node_data_[byte_offset]);
300+
if (instance_node->IsInactive())
265301
{
266302
++inactive_count;
267303
}
304+
305+
byte_offset += GetInstanceNodeSize();
268306
}
269307
return inactive_count;
270308
}
@@ -361,20 +399,16 @@ namespace rta
361399

362400
float EncodedRtIp11TopLevelBvh::GetLeafNodeSurfaceAreaHeuristic(const dxr::amd::NodePointer node_ptr) const
363401
{
364-
const uint32_t byte_offset = node_ptr.GetByteOffset();
365-
const uint32_t leaf_nodes = GetHeader().GetBufferOffsets().leaf_nodes;
366-
const uint32_t index = (byte_offset - leaf_nodes) / sizeof(dxr::amd::InstanceNode);
367-
assert(index < instance_nodes_.size());
402+
const uint32_t index = GetInstanceIndex(&node_ptr);
403+
assert(index != -1);
368404
assert(index < instance_surface_area_heuristic_.size());
369405
return instance_surface_area_heuristic_[index];
370406
}
371407

372408
void EncodedRtIp11TopLevelBvh::SetLeafNodeSurfaceAreaHeuristic(const dxr::amd::NodePointer node_ptr, float surface_area_heuristic)
373409
{
374-
const uint32_t byte_offset = node_ptr.GetByteOffset();
375-
const uint32_t leaf_nodes = GetHeader().GetBufferOffsets().leaf_nodes;
376-
const uint32_t index = (byte_offset - leaf_nodes) / sizeof(dxr::amd::InstanceNode);
377-
assert(index < instance_nodes_.size());
410+
const uint32_t index = GetInstanceIndex(&node_ptr);
411+
assert(index != -1);
378412
assert(index < instance_surface_area_heuristic_.size());
379413
instance_surface_area_heuristic_[index] = surface_area_heuristic;
380414
}

‎source/backend/bvh/encoded_rt_ip_11_top_level_bvh.h

+21-6
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2021-2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief RT IP 1.1 (Navi2x) specific top level acceleration structure
@@ -28,10 +28,19 @@ namespace rta
2828
/// @brief Destructor.
2929
virtual ~EncodedRtIp11TopLevelBvh();
3030

31-
/// @brief Get the instance nodes.
31+
/// @brief Get an instance node from an instance node pointer.
3232
///
33-
/// @return The instance nodes.
34-
const std::vector<dxr::amd::InstanceNode>& GetInstanceNodes() const;
33+
/// @param [in] node_ptr The instance node pointer.
34+
///
35+
/// @return Pointer to the instance node, or nullptr if instance node is invalid.
36+
const dxr::amd::InstanceNode* GetInstanceNode(const dxr::amd::NodePointer* node_ptr) const;
37+
38+
/// @brief Get the index of an instance node from an instance node pointer.
39+
///
40+
/// @param [in] node_ptr The instance node pointer.
41+
///
42+
/// @return The instance index, or -1 if the index is invalid.
43+
int32_t GetInstanceIndex(const dxr::amd::NodePointer* node_ptr) const;
3544

3645
/// @brief Does this BVH have references.
3746
///
@@ -133,6 +142,13 @@ namespace rta
133142
void SetLeafNodeSurfaceAreaHeuristic(const dxr::amd::NodePointer node_ptr, float surface_area_heuristic);
134143

135144
private:
145+
/// @brief Get the size of an instance node.
146+
///
147+
/// This will be dependent on whether it's a fused instance or not.
148+
///
149+
/// @return The instance node size, in bytes.
150+
std::int32_t GetInstanceNodeSize() const;
151+
136152
/// @brief Obtain the byte size of the encoded buffer.
137153
///
138154
/// @param [in] import_option Flag indicating which sections of the chunk to load/discard.
@@ -150,8 +166,7 @@ namespace rta
150166
/// @return The number of inactive instances.
151167
virtual uint64_t GetInactiveInstanceCountImpl() const override;
152168

153-
std::vector<dxr::amd::InstanceNode> instance_nodes_ = {}; ///< The list of instance nodes.
154-
std::vector<dxr::amd::NodePointer> primitive_node_ptrs_ = {}; ///< The list of primitive node pointers.
169+
std::vector<std::uint8_t> instance_node_data_ = {}; ///< The list of instance nodes.
155170
std::unordered_map<uint64_t, std::vector<dxr::amd::NodePointer>> instance_list_ = {}; ///< A map of BLAS index to list of instances of that BLAS.
156171
std::vector<float> instance_surface_area_heuristic_ = {}; ///< Surface area heuristic values for the instances.
157172
};

‎source/backend/bvh/flags_util.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2021 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief Header for flag, bitfield and bit magic helpers that do not depend

‎source/backend/bvh/geometry_info.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief Implementation of the geometry info class.

‎source/backend/bvh/geometry_info.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief Definition for the geometry info class.

‎source/backend/bvh/gpu_def.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2021-2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief Header for miscellaneous GPU definitions.

‎source/backend/bvh/ibvh.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//=============================================================================
2-
// Copyright (c) 2021-2022 Advanced Micro Devices, Inc. All rights reserved.
2+
// Copyright (c) 2021-2023 Advanced Micro Devices, Inc. All rights reserved.
33
/// @author AMD Developer Tools Team
44
/// @file
55
/// @brief BVH base class implementations.

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