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RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100
Shenzhen Metro: Metro Management System - Database and API Design Projects - SUSTech's projects of course CS307: Principles of Database System in Spring 2024 - Scores: 95/100 for Project 1 and 102/…
SUSSYCourses: Role-based OpenCourseWare Web App in Vue.js + Spring Boot - SUSTech project of CS309: Object-oriented Analysis and Design in Fall 2024 - Score: 100/100