CogVm source as per VMMaker.oscog-eem.3117

eliotmiranda · eliotmiranda · commit 6f2914e4484f · 2021-12-02T14:03:25.000-08:00
Cog ARMv8: Since id_aa64isar0_el1 is a priviledged instruction use getauxval on linux to derive the value(s) derived there-from, currenty whether atomic instructions are available or not. This addresses opensmalltalk-vm Issue #608.
diff --git a/src/spur64.cog/cogit.h b/src/spur64.cog/cogit.h
@@ -1,5 +1,5 @@
 /* Automatically generated by
-	CCodeGenerator VMMaker.oscog-eem.3116 uuid: d757936e-c3f3-48be-9435-9a3a60b14615
+	CCodeGenerator VMMaker.oscog-eem.3117 uuid: ede3f763-e691-4662-91d0-34fc19bc39a1
  */
 
 
diff --git a/src/spur64.cog/cogitARMv8.c b/src/spur64.cog/cogitARMv8.c
@@ -1,9 +1,9 @@
 /* Automatically generated by
-	CCodeGenerator VMMaker.oscog-eem.3114 uuid: 0522972d-531d-4f3a-9559-5c9bdbbf5427
+	CCodeGenerator VMMaker.oscog-eem.3117 uuid: ede3f763-e691-4662-91d0-34fc19bc39a1
    from
-	StackToRegisterMappingCogit VMMaker.oscog-eem.3114 uuid: 0522972d-531d-4f3a-9559-5c9bdbbf5427
+	StackToRegisterMappingCogit VMMaker.oscog-eem.3117 uuid: ede3f763-e691-4662-91d0-34fc19bc39a1
  */
-static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-eem.3114 uuid: 0522972d-531d-4f3a-9559-5c9bdbbf5427 " __DATE__ ;
+static char __buildInfo[] = "StackToRegisterMappingCogit VMMaker.oscog-eem.3117 uuid: ede3f763-e691-4662-91d0-34fc19bc39a1 " __DATE__ ;
 char *__cogitBuildInfo = __buildInfo;
 
 
@@ -27,8 +27,11 @@ char *__cogitBuildInfo = __buildInfo;
 
 
 /* Cogit class>>preambleCCode */
-#if __APPLE__ && __MACH__ /* Mac OS X */
-#include <libkern/OSCacheControl.h>
+#if __APPLE__ && __MACH__ // Mac OS X
+# include <libkern/OSCacheControl.h>
+#endif
+#if __linux__
+# include <sys/auxv.h>
 #endif
 /* end Cogit class>>preambleCCode */
 
@@ -568,12 +571,15 @@ static sqInt NoDbgRegParms countLeadingOnes(AbstractInstruction * self_in_countL
 static sqInt NoDbgRegParms countTrailingOnes(AbstractInstruction * self_in_countTrailingOnes, sqInt anInteger);
 static sqInt NoDbgRegParms countTrailingZeros(AbstractInstruction * self_in_countTrailingZeros, sqInt anInteger);
 static usqInt NoDbgRegParms decode64Immsimmr(AbstractInstruction * self_in_decode64Immsimmr, sqInt imms, sqInt immr);
-#if !__APPLE__
+#if __linux__
 static void NoDbgRegParms detectFeaturesOnLinux(AbstractInstruction * self_in_detectFeaturesOnLinux);
-#endif /* !__APPLE__ */
+#endif /* __linux__ */
 #if __APPLE__
 static void NoDbgRegParms detectFeaturesOnMacOS(AbstractInstruction * self_in_detectFeaturesOnMacOS);
 #endif /* __APPLE__ */
+#if !__APPLE__ && !__linux__
+static void NoDbgRegParms detectFeaturesOnRawMachine(AbstractInstruction * self_in_detectFeaturesOnRawMachine);
+#endif /* !__APPLE__ && !__linux__ */
 static sqInt NoDbgRegParms dispatchConcretize(AbstractInstruction * self_in_dispatchConcretize);
 static sqInt NoDbgRegParms emitLdfprnrtimmshiftBy12at(AbstractInstruction * self_in_emitLdfprnrtimmshiftBy12at, sqInt baseReg, sqInt targetDPReg, sqInt offset, sqInt shiftBy12, sqInt instrOffset);
 static sqInt NoDbgRegParms emitLdrnrtimmshiftBy12at(AbstractInstruction * self_in_emitLdrnrtimmshiftBy12at, sqInt unitSizeLog2MinusOne, sqInt baseReg, sqInt targetReg, sqInt offset, sqInt shiftBy12, sqInt instrOffset);
@@ -4290,19 +4296,19 @@ decode64Immsimmr(AbstractInstruction * self_in_decode64Immsimmr, sqInt imms, sqI
 }
 
 
-/*	Do throw-away compilations to read CTR_EL0 & ID_AA64ISAR0_EL1 and
-	initialize ctrEl0 & idISAR0
- */
+/*	Do a throw-away compilation to read CTR_EL0 and initialize ctrEl0.
+	Some linux kernels trap and synthesize access to ID_AA64ISAR0_EL1,
+	and some do not, so use getauxval(3) to access value(s) derived
+	there-from, i.e. whether the processor has atomic instructions. */
 
 	/* CogARMv8Compiler>>#detectFeaturesOnLinux */
-#if !__APPLE__
+#if __linux__
 static void NoDbgRegParms
 detectFeaturesOnLinux(AbstractInstruction * self_in_detectFeaturesOnLinux)
 {
     sqInt ctrEL0;
     sqInt fixupSize;
     usqIntptr_t (*getFeatureReg)(void);
-    sqInt idISAR0;
     sqInt opcodeSize;
     usqInt startAddress;
 
@@ -4355,32 +4361,9 @@ detectFeaturesOnLinux(AbstractInstruction * self_in_detectFeaturesOnLinux)
 	if ((instructionCacheLineLength(self_in_detectFeaturesOnLinux)) == 0) {
 		setInstructionCacheLineLength(self_in_detectFeaturesOnLinux, 64);
 	}
-	zeroOpcodeIndexForNewOpcodes();
-	gen(Nop);
-	genoperand(MRS_ID_AA64ISAR0_EL1, ABIResultReg);
-	genoperand(RetN, 0);
-	outputInstructionsForGeneratedRuntimeAt(startAddress);
-	/* begin resetMethodZoneBase: */
-	methodZoneBase = startAddress;
-	/* begin ensureExecutableCodeZoneWithin: */
-	
-#  if !DUAL_MAPPED_CODE_ZONE
-	/* begin makeCodeZoneExecutable */
-#  if __APPLE__ && __MACH__
-	pthread_jit_write_protect_np(1);
-#  endif
-#  endif
-	idISAR0 = getFeatureReg();
-	setHasAtomicInstructions(self_in_detectFeaturesOnLinux, ((((usqInt)(idISAR0)) >> 20) & 15) == 2);
-	/* begin ensureWritableCodeZone */
-#  if !DUAL_MAPPED_CODE_ZONE
-	/* begin makeCodeZoneWritable */
-#  if __APPLE__ && __MACH__
-	pthread_jit_write_protect_np(0);
-#  endif
-#  endif
+	setHasAtomicInstructions(self_in_detectFeaturesOnLinux, (((getauxval(AT_HWCAP)) & HWCAP_ATOMICS) != 0));
 }
-#endif /* !__APPLE__ */
+#endif /* __linux__ */
 
 
 /*	MacOS does not allow access to ctl_el0, so derive cache information etc
@@ -4408,6 +4391,99 @@ detectFeaturesOnMacOS(AbstractInstruction * self_in_detectFeaturesOnMacOS)
 #endif /* __APPLE__ */
 
 
+/*	Do throw-away compilations to read CTR_EL0 & ID_AA64ISAR0_EL1 and
+	initialize ctrEl0 & idISAR0
+ */
+
+	/* CogARMv8Compiler>>#detectFeaturesOnRawMachine */
+#if !__APPLE__ && !__linux__
+static void NoDbgRegParms
+detectFeaturesOnRawMachine(AbstractInstruction * self_in_detectFeaturesOnRawMachine)
+{
+    sqInt ctrEL0;
+    sqInt fixupSize;
+    usqIntptr_t (*getFeatureReg)(void);
+    sqInt idISAR0;
+    sqInt opcodeSize;
+    usqInt startAddress;
+
+	startAddress = methodZoneBase();
+	/* begin allocateOpcodes:bytecodes: */
+	numAbstractOpcodes = 4;
+	opcodeSize = (sizeof(CogAbstractInstruction)) * numAbstractOpcodes;
+	fixupSize = (sizeof(CogBytecodeFixup)) * numAbstractOpcodes;
+	abstractOpcodes = alloca(opcodeSize + fixupSize);
+	bzero(abstractOpcodes, opcodeSize + fixupSize);
+	fixups = ((void *)((((usqInt)abstractOpcodes)) + opcodeSize));
+	zeroOpcodeIndexForNewOpcodes();
+	labelCounter = 0;
+
+	/* Return the value of CTR_EL0; that's the control register that defines the vital statistics of the processor's caches. */
+	getFeatureReg = ((usqIntptr_t (*)(void)) startAddress);
+	gen(Nop);
+	genoperand(MRS_CTR_EL0, ABIResultReg);
+	genoperand(RetN, 0);
+	outputInstructionsForGeneratedRuntimeAt(startAddress);
+	/* begin resetMethodZoneBase: */
+	methodZoneBase = startAddress;
+	/* begin ensureExecutableCodeZoneWithin: */
+	
+#  if !DUAL_MAPPED_CODE_ZONE
+	/* begin makeCodeZoneExecutable */
+#  if __APPLE__ && __MACH__
+	pthread_jit_write_protect_np(1);
+#  endif
+#  endif
+	
+	/* see e.g. CogARMv8Compiler class>>printCTR_EL0:, concretizeCacheControlOp1:CRm:Op2: &
+	   http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100403_0200_00_en/lau1443435580346.html
+	   DminLine & IminLine are Log2 words; 16 words miniumum */
+	ctrEL0 = getFeatureReg();
+	setDataCacheFlushRequired(self_in_detectFeaturesOnRawMachine, (!(ctrEL0 & (0x10000000))));
+	setDataCacheLineLength(self_in_detectFeaturesOnRawMachine, 4ULL << ((((usqInt)(ctrEL0)) >> 16) & 15));
+	if ((dataCacheLineLength(self_in_detectFeaturesOnRawMachine)) == 0) {
+		setDataCacheLineLength(self_in_detectFeaturesOnRawMachine, 64);
+	}
+	setInstructionCacheFlushRequired(self_in_detectFeaturesOnRawMachine, (!(ctrEL0 & (0x20000000))));
+	setInstructionCacheLineLength(self_in_detectFeaturesOnRawMachine, 4ULL << (ctrEL0 & 15));
+	/* begin ensureWritableCodeZone */
+#  if !DUAL_MAPPED_CODE_ZONE
+	/* begin makeCodeZoneWritable */
+#  if __APPLE__ && __MACH__
+	pthread_jit_write_protect_np(0);
+#  endif
+#  endif
+	if ((instructionCacheLineLength(self_in_detectFeaturesOnRawMachine)) == 0) {
+		setInstructionCacheLineLength(self_in_detectFeaturesOnRawMachine, 64);
+	}
+	zeroOpcodeIndexForNewOpcodes();
+	gen(Nop);
+	genoperand(MRS_ID_AA64ISAR0_EL1, ABIResultReg);
+	genoperand(RetN, 0);
+	outputInstructionsForGeneratedRuntimeAt(startAddress);
+	/* begin resetMethodZoneBase: */
+	methodZoneBase = startAddress;
+	/* begin ensureExecutableCodeZoneWithin: */
+	
+#  if !DUAL_MAPPED_CODE_ZONE
+	/* begin makeCodeZoneExecutable */
+#  if __APPLE__ && __MACH__
+	pthread_jit_write_protect_np(1);
+#  endif
+#  endif
+	idISAR0 = getFeatureReg();
+	setHasAtomicInstructions(self_in_detectFeaturesOnRawMachine, ((((usqInt)(idISAR0)) >> 20) & 15) == 2);
+	/* begin ensureWritableCodeZone */
+#  if !DUAL_MAPPED_CODE_ZONE
+	/* begin makeCodeZoneWritable */
+#  if __APPLE__ && __MACH__
+	pthread_jit_write_protect_np(0);
+#  endif
+#  endif
+}
+#endif /* !__APPLE__ && !__linux__ */
+
+
 /*	Attempt to generate concrete machine code for the instruction at address.
 	This is the inner dispatch of concretizeAt: actualAddress which exists
 	only to get around the branch size limits in the SqueakV3 (blue book
@@ -7284,7 +7360,7 @@ rewriteImm19JumpBeforetarget(AbstractInstruction * self_in_rewriteImm19JumpBefor
 static sqInt NoDbgRegParms
 rewriteImm26JumpBeforetarget(AbstractInstruction * self_in_rewriteImm26JumpBeforetarget, sqInt followingAddress, sqInt targetAddress)
 {
-    usqInt instrOpcode;
+    sqInt instrOpcode;
     sqInt mcpc;
     sqInt offset;
 
@@ -7294,7 +7370,7 @@ rewriteImm26JumpBeforetarget(AbstractInstruction * self_in_rewriteImm26JumpBefor
 	instrOpcode = ((instructionBeforeAddress(self_in_rewriteImm26JumpBeforetarget, followingAddress))) >> 26;
 	assert((instrOpcode == 5)
 	 || (instrOpcode == 37));
-	codeLong32Atput(mcpc, (instrOpcode << 26) + (((offset) >> 2) & (0x3FFFFFF)));
+	codeLong32Atput(mcpc, (((sqInt)((usqInt)(instrOpcode) << 26))) + (((offset) >> 2) & (0x3FFFFFF)));
 	return 4;
 }
 
@@ -13162,8 +13238,12 @@ initializeCodeZoneFromupTo(sqInt startAddress, sqInt endAddress)
 #  if __APPLE__
 	detectFeaturesOnMacOS(((AbstractInstruction *) backEnd));
 #  else
+#  if __linux__
 	detectFeaturesOnLinux(((AbstractInstruction *) backEnd));
+#  else
+	detectFeaturesOnRawMachine(((AbstractInstruction *) backEnd));
 #  endif
+#  endif // __APPLE__
 	/* begin maybeGenerateCacheFlush */
 	if ((numICacheFlushOpcodes(backEnd)) > 0) {
 		/* begin allocateOpcodes:bytecodes: */
diff --git a/src/spur64.sista/cogit.h b/src/spur64.sista/cogit.h
@@ -1,5 +1,5 @@
 /* Automatically generated by
-	CCodeGenerator VMMaker.oscog-eem.3116 uuid: d757936e-c3f3-48be-9435-9a3a60b14615
+	CCodeGenerator VMMaker.oscog-eem.3117 uuid: ede3f763-e691-4662-91d0-34fc19bc39a1
  */
 
 
diff --git a/src/spur64.sista/cogitARMv8.c b/src/spur64.sista/cogitARMv8.c
