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If the relocation calculation for the different types of relocations is really the same for all architectures, I think the solution you proposed with the prefixes I also like the fact that no additional keyword is required for the pseudo-command overload, but that it is determined from the relocations used! Question: How do you know that the Slightly off topic: Why are relocation definitions in VADL part of the ISA and not the ABI? |
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@AndreasKrall did you make your mind about this? Can we make new keywords or annotations? |
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I checked vadl.ATG. |
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Both RISCV-64 and Aarch64 require PIC (Position Independent Code) to be executed. So far, this hasn't been something that VADL can support.
Overall, I can summarize when PIC affects three areas: global variables, functions, pseudo instructions and assembly parser.
A good introduction gives https://eli.thegreenplace.net/2011/11/03/position-independent-code-pic-in-shared-libraries/.
Summary
Global Variables
But here is a gentle summary. With None Position Independent Code, the symbols are stored directly into an instruction with relocations. The linker then resolves all relocations at link-time and updates the immediate to store the final address. With PIC, the absolute addresses are stored in a separate ELF section called
got(Global Offset Table). The GOT contains the absolute addresses to the symbols. So all the immediates refer to thegotaddress instead of the absolute address.Functions
Addresses to functions are only known at load-time. So, function calls do not call an absolute address but instead a PLT (Procedure Linkage Table) which resolves the address and then caches it in
got.Pseudo Instructions:
The pseudo instruction
LAchanges its behavior with PIC. In the Non-PIC version, it calculatessymbol - PCwhile with PICGOT[symbol] - pc.Additionally, there are more relocations which have to be supported for PIC e.g.
GOT_HI20,PCREL_HI20,PCREL_LO12_IandPCREL_LO12_S.Implementation
Currently, the relocation in VADL looks like this
relocation hi( symbol : Bits<32> ) -> UInt<20> = ( ( symbol + 0x800 as Bits<32> ) >> 12 ) as UInt<20>. With PIC more keywords are required to calculate the address. A list of keywords which need to be supported can be found https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#calculation-symbols here.hiit is0x800Assembler Printer / Assembler Parser
The assembler printer (and assembler parser) needs to support the
.option PICwhich indicates that the assembly was generated with PIC. Like mentioned below, we need also to support@pltsuffixes for function calls.Some useful links:
https://reviews.llvm.org/D55325
Data Relocations
Compiler
The LCB has to define modifiers for all the defined relocations like
hi,lo,pcrel_hi,pcrel_lo,got_hi. These need to be mapped to variant kinds, and then to fixups. Finally, the fixups need to be mapped to relocations. Since VADL is more generic then RISC-V, we cannot assume that there is only one immediate in one instruction. Therefore at some point there is a1:nrelationship. The1:nis between variant kinds and fixups. Each fixup represents one field in a format that has to be updated.But how does the compiler choose whether it needs the
loorpcrel_lorelocation?RISC-V defines multiple pseudo instructions to load addresses e.g.
PseudoLGAorPseudoLA. The instruction itself is not chosen by the instruction selection but with custom methods in ISelLowering. The pseudo expansion then lowers the modifier in Emit MO_GOT_HI.The pseudo instruction
LAbelow defines the loading of an address. The compiler can determine whether the pseudo instruction is an absolute pseudo instruction by checking that only absolute relocations are used. Likewise, a relative pseudo instruction can use relative relocations (which use pc) or got relocations (which use got).The patch for supporting the
pcrelis defined here https://github.com/lowRISC/riscv-llvm/blob/master/0082-RISCV-Add-support-for-pcrel_lo.patch.Linker
The extension to the linker is not trivial. As defined in the linked discussion, the calculation is splitted across two methods.
First, the entrypoint is in
relocateAlloc.The getRelocTargetVA method itself calculates the value for the relocation with
pcorgotfor all architectures. While, the relocate function will apply the addendum0x800and shifting. This is vastly different then we implemented relocations so far, since we directly generated C++ code from the VADL's relocation specification. From my point of view, it makes sense to split relocations up.Since, they are all the same for all architectures, we do not need the PC and GOT calculation itself. We just keep the addendum calculation and translate it as we did before. The only thing that is left to implement is the mapping from a target specific relocations to a generic LLVM relocation. We already do that and an extension is easy. See RISC-V
Call Relocations
The sections before mentioned only static data relocations. Data relocations are for global variables. However, function calls for absolute addresses (non-pic) work exactly like data relocations and nothing has to be changed. When comes to PIC, data relocations and call relocations differ from each other.
The assembly printer needs an extension to print the suffix
@plt. The assembly parser has also to support it. Additionally,LowerCallneeds to emit the modifier when it is an external symbol. See here. Finally, we need to map the target specific relocation to a generic LLVM relocation. See RISC-VUseful links:
https://reviews.llvm.org/D63076
Notes for Aarch64
One of the major differences between RISC-V' and Aarch64's relocations is that Aarch64 focuses on partial writes. Static Relocations.
This was presented on 12.03.2025 at the VADL meeting. One of the criticized points is that
absolute,relativeandgotmust be reserved as keywords. An alternative would be to use annotation instead and just keep therelocationkeyword as the only keyword. @AndreasKrall will think about it.Beta Was this translation helpful? Give feedback.
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