How to specify instruction variants with expressions with null elements

[AndreasKrall]

In the AArch64 spec there are many instructions with variants where the variant has no effect as it is an algebraic zero element, e.g. a shift or rotate by 0.
An example are the logic instructions like and or or where the the second source register can be shifted or rotated by the shift amount specified in imm6. When the ShiftType is LSL and imm6 is zero currently an own instruction without the shift in the logical expression and a simplified assembler syntax is generated.

($modelid; $i; ""   ; $size; (X(rm) as Bits<Size::$size>; imm6 = 0, shift = ShiftType::LSL;  $size(rm))) // TODO pseudo instruction
($modelid; $i; "LSL"; $size; (X(rm) as Bits<Size::$size>  << imm6;  shift = ShiftType::LSL; ($size(rm), ", lsl #", decimal(imm6))))
($modelid; $i; "LSR"; $size; (X(rm) as UInt<Size::$size>  >> imm6;  shift = ShiftType::LSR; ($size(rm), ", lsr #", decimal(imm6))))
($modelid; $i; "ASR"; $size; (X(rm) as SInt<Size::$size>  >> imm6;  shift = ShiftType::ASR; ($size(rm), ", asr #", decimal(imm6))))
($modelid; $i; "ROR"; $size; (X(rm) as Bits<Size::$size> <>> imm6;  shift = ShiftType::ROR; ($size(rm), ", ror #", decimal(imm6))))

For the other shift types (LSR, ASR and ROR) no special variants are generated.

How should the preferred specification be. There are possibilities to specify pseudo instructions with the special assembly syntax. No variants at all, but assembly string functions which generate the preferred syntax.
How will the generators optimize the instructions where no variants for 0 are specified.
Will the QEMU generator generate instructions without shift? Can the compiler generator derive both variants? Can the hardware generate a one stage pipeline for the 0 variant and a 2 stage pipeline for the other variants? Can the instruction scheduler in the compiler and the cycle approximate simulator derive the correct latency and generate the necessary scheduler and the scoreboard for the simulator?

[AndreasKrall]

In the meeting on May 21st we decided that in the future both the compiler and simulator generator will support the optimization or required splitting of such expressions. Until these optimizations are implemented the special versions have to be specified using macros as currently done.

[Jozott00]

For context: QEMU is able to optimize such variants by itself. It can do it at two phases: In the TCG opcode generation, if the shift amount parameter is constant (which is the case for format fields) and at host machine code generation time.
So for the ISS no further optimizations are required.