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Description
PPC64 uses a single 32-bit condition register. This register requires dynamic indexing of both individual bits and 4-bit fields. There are two ways to implement this.
The first is with relational alias types:
register CR : Bits<32> // needed for comparison with upstream
alias register CRF : Bits<3> -> Bits<4> = CR // field access
alias register CRB : Bits<32> -> Bits<1> = CR // bit access
The second is with dynamic tensor indexing:
register CR : Bits<32> // bit access
alias register CRF : Bits<8><4> = CR // field access
Relational alias types support dynamic indexing, but don't support the aliases as written above. Option 2 doesn't work because tensor indexing must be a constant value.
Example with dynamic tensor indexing:
instruction set architecture ARCH = {
program counter PC : Bits<64>
memory MEM : Bits<64> -> Bits<8>
register CR : Bits<32> // bit access
alias register CRF : Bits<8><4> = CR // field access
format TestForm : Bits<32> =
{ opcd : Bits<24>
, index_bit : Bits<5>
, index_field : Bits<3>
}
instruction instr : TestForm =
CRF(index_field) := 0xF // or CR(index_bit) := 0b1
encoding instr = {opcd = 1 as Bits<24>}
assembly instr = ("testinstr")
}
processor EXAMPLE implements ARCH = {
reset = PC := 0x0000'0000'0000'0000
[ firmware ]
[ base: 0x00000000 ]
memory region [RAM] DRAM in MEM
}
causes this error:
error: Invalid constant value
╭──[file:///_/openvadl/sys/ppc64/issue.vadl:16:9]
│
16 │ CRF(index_field) := 0xF // or CR(index_bit) := 0b1
│ ^^^^^^^^^^^ Cannot evaluate identifier with origin of vadl.ast.TypedFormatField
│
Tensor indexing must be a constant value.
Either option works, but it’s unclear to me which is easier to implement.
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enhancementNew feature or requestNew feature or requestfrontendThis is frontend relatedThis is frontend relatedissThis is ISS relatedThis is ISS related