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Integrate VDT into the RTL synthesis #560

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Integrate VDT into the RTL synthesis #560

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@rascmatt rascmatt commented Nov 9, 2025

Changes introduced within this PR:

  • Extend the IPG with a RtlDecodeTreeNode, to represent the decoder in the RTL IPG + Behavior graphs
  • Extract the control signals decided/decoded by the decode tree based on instruction context in the IPG
  • Optionally emit the VDT or a truth-table based decoder
  • Introduce a new CLI option rtl-table to optionally select table-based decoder

@rascmatt
decoder: Draft the chisel decoder generator
2b0dc4f 
- Implement generator to represent the decision
  logic of the decode tree as a Chisel module
@rascmatt
decoder: Add option to utilize Chisel's decoder library
48f34e7 
- For fixed-length, non-overlapping instruction sets,
  we may use Chisel's truth/decoder table with circuit
  optimizations to generate a decoder
@rascmatt
decoder: Rebase/Update implementation
d5d28ab
@rascmatt
Introduce decode tree node to the IPG
00f44df
@rascmatt
Implement the HDL lowering of the decode tree node
f65bfe4
@rascmatt
Implement HDL lowering for irregular VDTs
efb2f31 
- add decoder option for the RTL table based
  decoder

- improve the RTL template formatting
@rascmatt rascmatt self-assigned this Nov 9, 2025
@rascmatt rascmatt requested a review from linushdot November 9, 2025 09:22
@github-actions github-actions bot added enhancement New feature or request hardware Related to the MiA and hardware generation labels Nov 9, 2025
@rascmatt rascmatt requested a review from Jozott00 November 9, 2025 09:22
@rascmatt rascmatt marked this pull request as ready for review November 9, 2025 09:23
Jozott00
Jozott00 approved these changes Nov 10, 2025
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LGTM

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@Jozott00 Jozott00 Jozott00 approved these changes

@linushdot linushdot Awaiting requested review from linushdot

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@rascmatt @Jozott00