rtl: HW Generation with new VIAM from Frontend#709
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flofriday
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I know this is just a draft but I got curious. 😅
I mostly looked over the frontend but it looks quite good.
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Models the new VIAM stage effects as a series of mapping contexts that feed into the instruction outputs of stages.
This makes all RTL passes take the ISA from the MiA definition. For the general VIAM passes to consider the ISA, the VIAM returns the ISA referenced by the MiA, if there is no top-level ISA definition.
Fix some bugs found through the tests.
C++ memory model for verilator simulation that can load ELF files. The emitted Chisel project can now run the simulator directly on riscv-tests ELF files without providing the memory in a Chisel test.
Fix some bugs (faulty forwarding/control logic)
Add select and unary nodes nodes that only depend on done nodes and compute nodes to compute.
New faster simulator with C++ memory model
Introduced to simplify the control logic
Also fixes type checker for some instruction map calls that do not require arguments. Change RtlEmitMinimizedRiscVTest to use the correct specification
In case a ISA definition is referenced from multiple definitions, e.g., from a processor and a MiA definition, it is visited and merged only once by caching the result in the definition cache.
Path separator and line ending problems
The spec now uses a macro model to select the ISA to use. Also include the single, three and five stage spec in the frontend tests.
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Introduces some minor frontend changes to make the current MiA specs work
This should also solve the problems discussed here #622