[RV32I46F_5SP] CSR File RAW Hazard

[T410N]

Problem Background

Revising Asynchronous CSR File to Synchronous occurs RAW pipeline hazard issue.

• [Feat] Revise RV32I46F_5SP by implementing Synchronous CSR File in top module design and its testebench #154

Problem Description

When consecutive Zicsr instructions access the same CSR address,
the updated CSR value from the preceding instruction should be forwarded to subsequent instructions.

While forwarding from MEM to EX stage for ALU calculations is already implemented, forwarding from retired instruction's value to the WB (Write-Back) stage remains problematic.

Future Improvement Plan

Currently, as the priority is on implementing I/O and benchmarking performance—and the CSR instructions in question are not utilized for these purposes—this issue is temporarily deferred.
This specific issue(CSR RAW Hazard issue) will be addressed in the near future, when project development schedules allow.

[ChoiCube84]

By the way, I think we don't need to put headers in the titles. Let's just name it CSR File RAW hazard occurs in the RV32I46F_5SP.