[RV32I46F_5SP] Instruction Memory's Misaligned Store & Load's Trap Handler scenario issue

[T410N]

Problem Background

Revising Misaligned Memory Access in Exception Detector to separate handling. To Misaligned Store and Misaligned Load.
Revising Core testbench scenarios integrated in Instruction Memory for verifying separated Misaligned Store and Misaligned Load by extending the Trap Handler routine.

• [Feat] Revise Exception Detector to separately handle MISALIGNED STORE and LOAD exceptions #148
• [Feat] Revise Instruction Memory by adding Misaligned store load trap handler and test expectation values #152

Problem Description

While verifying the total logics on FPGA, it showed unexpected behavior such as stalling and resetting register value to 0 after the misaligned store exception.

Future Improvement Plan

Since the deadline is near, I decided to delay resolving this issue.
Temporarily for now, we brought back the old Instruction Memory's integrated Core testbench scenario in PR #177.

• [Feat] Revise Instruction Memory by bringing back old testbenches #177

Currently, as the priority is on implementing I/O and benchmarking Dhrystone performance—and the misaligned exception in question are not utilized for these purposes—this issue is temporarily deferred.
This specific issue(Instruction Memory's Misaligned Store & Load's Trap Handler scenario issue) will be addressed in the near future, when project development schedules allow.