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…64860) Add declarations/includes of Scope and Symbol to Semantics/openmp-utils.
This patch fixes: llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1643:9: error: unused variable 'T2SOImmVal' [-Werror,-Wunused-variable]
Similar to other code in ADT / STLExtras, allow `to_vector` to work with ranges that require ADL to find the begin/end iterators.
…vm#164716) Print a note when the manually specified name in an intrinsic matches the default name it would have been assigned based on the record name, in which case the manual specification is redundant and can be eliminated. Also remove existing redundant manual names.
…lvm#164870) Rename OmpTypeSpecifier to OmpTypeName, since it represents a type-name list item. Also, OpenMP 6.0 introduced type-specifier with a different meaning. Rename OmpReductionCombiner to OmpCombinerExpression.
…llvm#164859) Use the new HasLocal flag to avoid looking through all summaries to see if there is a local copy.
Move a loop invariant check out of the innermost loop. I measured a small but consistent thin link speedup from this change for a large target (0.75%).
This always makes the StatusOr OK. Reviewers: jvoung, Xazax-hun Reviewed By: jvoung Pull Request: llvm#163876
…m#164759) These instructions are FP instructions with SEW=8. vtype.altfmt=1 should be considered reserved for them.
Unaligned atomic vectors with size >1 are lowered to calls. Adding their tests separately here.
…vm#164865) When lowering `atomiccas`, flang does not convert the output of the `llvm.extract_value` op to result type expected in the expression being lowered. This results in invalid MLIR being generated such as when the output of the atomiccas is being used for an equality check in a `do while` loop condition, where the `arith.cmpi` would be comparing an `i64 0` with an `i1`. This change ensures that the appropriate cast is inserted. Reviewers: @clementval @vzakhari
Cleanly make 32-bit abs legal only in SIISelLowering.cpp Signed-off-by: John Lu <John.Lu@amd.com>
Downloads clang-for-windows from the LLVM releases website, decompresses and untars the images, and leave them in C:\clang\clang-msvc\... Temporarily downloads the 'xz' utility to decompress the downloaded clang tarball image.
This reverts commit faf7af8. This is failing on the Darwin bots. https://green.lab.llvm.org/job/llvm.org/view/LLDB/job/lldb-cmake/16164/changes#faf7af864f9258768133894764f1fae58d43bb09
Add support for MIR (Machine IR) triplet generation to the triplet gen script.
chunk enumeartions. Noticed by David Spickett. NFC--no machine with a ZA register large enough to use this exists today.
Add additional test coverage for narrowInterleaveGroups with loops with multiple blocks.
) This introduces the Armv9.7-A architecture version, including the relevant command-line option for -march. More details about the Armv9.7-A architecture version can be found at: * https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2025 * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions * https://developer.arm.com/documentation/ddi0602/2025-09/ Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>
…vm#163155) Add the following instructions to support: * `FEAT_CMH`: Contention Management Hints extension * `SHUH` instruction * `FEAT_LSCP`: Load-acquire and store-release pair extension * `STLP` instruction * `LDAP` instruction * `LDAPP` instruction and system registers: - `TLBIDIDR_EL1` - `VTLBID<n>_EL2` - `VTLBIDOS<n>_EL2` as documented here: * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions * https://developer.arm.com/documentation/ddi0602/2025-09/ Co-authored-by: Martin Wehking <martin.wehking@arm.com>
…lvm#163156) Allow the following `TLBI` operation types to take an optional register operand when enabled by `FEAT_TLBID`: - ALL* - VMALL* - VMALLS12* - VMALLWS2* as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions Notes on implementation: Currently, AArch64 `SYS` alias instructions fall into two categories: * a register value must be present (indicated by any value except `XZR`) * no register value must be present (this value must be `XZR`) When +tblid is enabled, `SYS` aliases are now allowed to take an optional register, or no register as before. We need an extra tablegen flag to indicate if the register is optional or not (the existing "NeedsReg" flag is binary and not suitable; the register is either present or absent, not either for a specific TLBI operation) Don't produce an error message if the register operand is missing or unexpected, if it is specified as an optional register.
…nagement (FEAT_MPAMv2) (llvm#163157) Add new instructions and system registers for `FEAT_MPAMv2`: * MLBI ALLE1 * MLBI VMALLE1 * MLBI VPIDE1, <Xt> * MLBI VPMGE1, <Xt> as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions Co-authored-by: Caroline Concatto <caroline.concatto@arm.com>
…AT_MTETC) (llvm#163158) Add the following instructions for `FEAT_MTETC`, which is a part of `FEAT_VMTE` for Virtual Tagging: * `DC ZGBVA` * `DC GBVA` as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
…3159) Add new instruction and system registers that are specified in the Generic Interrupt Controller Architecture v5 (GICv5) standard, announced here: * https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/introducing-gicv5 and documented here: * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions * https://developer.arm.com/documentation/ddi0602/2025-09/ Co-authored-by: Jack Styles <jack.styles@arm.com>
The intermediate result is in fact the add with saturation regardless of the clamp bit.
We will need the full 16-bit range of the operand to record previous mode.
…ns (llvm#163160) Add instructions for SVE2p3 arithmetic operations: - `ADDQP` (add pairwise within quadword vector segments) - `ADDSUBP` (add subtract pairwise) - `SABAL` (two-way signed absolute difference sum and accumulate long) - `SUBP` (subtract pairwise) - `UABAL` (two-way unsigned absolute difference sum and accumulate long) as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
…ons (llvm#163161) Add instructions for SVE2p3 DOT and MLA operations: - BFMMLA (non-widening) - FMMLA (non-widening) - SDOT (2-way, vectors) - SDOT (2-way, indexed) - UDOT (2-way, vectors) - UDOT (2-way, indexed) as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
…m#163162) Add instructions for SVE2p3 CVT operations: - FCVTZSN - FCVTZUN - SCVTF - SCVTFLT - UCVTF - UCVTFLT as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
Currently only regions with a single block are supported by the legality checks.
…lvm#164528) In normal circumstances we can never get to this point as earlier Sema checks will have already have prevented us from making these queries. However in some cases, for example a sufficiently large number of errors, clang can start allowing incomplete types in records. This means a number of the internal interfaces can end up perform type trait queries that require querying the pointer authentication properties of types that contain incomplete types. While the trait queries attempt to guard against incomplete types, those tests fail in this case as the incomplete types are actually nested in the seemingly complete parent type.
…lvm#163163) Add instructions for SVE2p3 shift operations: - SQRSHRN - SQRSHRUN - SQSHRN - SQSHRUN - UQRSHRN - UQSHRN as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions
…lvm#163164) Add instructions for SVE2p3 LUTI6 operations: - LUTI6 (16-bit) - LUTI6 (8-bit) - LUTI6 (vector, 16-bit) - LUTI6 (table, four registers, 8-bit) - LUTI6 (table, single, 8-bit) as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions Co-authored-by: Virginia Cangelosi <virginia.cangelosi@arm.com>
…nstructions (llvm#163165) Add support for new Advanced SIMD (Neon) instructions: - FDOT (half-precision to single-precision, by element) - FDOT (half-precision to single-precision, vector) - FMMLA (half-precision, non-widening) - FMMLA (widening, half-precision to single-precision) as documented here: * https://developer.arm.com/documentation/ddi0602/2025-09/ * https://developer.arm.com/documentation/109697/2025_09/2025-Architecture-Extensions Co-authored-by: Kerry McLaughlin <kerry.mclaughlin@arm.com> Co-authored-by: Caroline Concatto <caroline.concatto@arm.com> Co-authored-by: Virginia Cangelosi <virginia.cangelosi@arm.com>
…63166) Remove `AArch64::FeatureMPAM` guards from some MPAM system registers, since these system registers are not any under feature guard for gcc.
…nfo.td (llvm#163645) It was noted in a code-review for earlier changes in this stack that some of the new 9.7 entries were mis-aligned. But actually, many of the entries were, so I've tidied them all up.
`FEAT_FPRCVT` is moved from being mandatory in Armv9.6-A to Armv9.7-A `FEAT_SVE2p2` is removed from being mandatory in Armv9.6-A
llvm#164906) The current code may trigger a compiler warning: ``` address of function 'wcsnlen' will always evaluate to 'true' [-Wpointer-bool-conversion] ``` Fix this by comparing to nullptr. The same fix is applied to strnlen for future-proofing.
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