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1262acf
Introduce DwarfUnit::addBlock helper method (#168446)
tromey Nov 18, 2025
0a96b24
[mlir][acc][flang] Introduce OpenACC interfaces for globals (#168614)
razvanlupusoru Nov 19, 2025
411c752
[orc-rt] Fix typos in file comments.
lhames Nov 19, 2025
651785a
Fix #168367 (#168635)
pranavk Nov 19, 2025
7819071
workflows/release-binaries: Drop install-ninja action (#167070)
tstellar Nov 19, 2025
c32d2ee
[NFC][TableGen] Adopt CodeGenHelpers in CodeGenMapTable (#168592)
jurahul Nov 19, 2025
88efd0e
[LTT] Mark as unkown weak function tests. (#167399)
mtrofin Nov 19, 2025
9a15556
[OpenACC] add cl::values to ACCImplicitRoutineOptions (#168601)
rscottmanley Nov 19, 2025
522177c
[NVPTX] Add a few more missing fence intrinsics (#166352)
schwarzschild-radius Nov 19, 2025
bfb9539
TableGen: Support target specialized pseudoinstructions (#159880)
arsenm Nov 19, 2025
961940e
[TTI] Use MemIntrinsicCostAttributes for getMaskedMemoryOpCost (#168029)
arcbbb Nov 19, 2025
a3ab110
[TableGen] Silence a warning (NFC)
DamonFool Nov 19, 2025
b4aa3d3
[NFC] Check operand type instead of opcode (#168641)
shiltian Nov 19, 2025
52a58a4
[AMDGPU] Adding instruction specific features (#167809)
Shoreshen Nov 19, 2025
5ee95f4
[AMDGPU][GlobalISel] Add regbankselect rules for G_FSHR (#159818)
gandhi56 Nov 19, 2025
52ed0f2
[SPARC][clang] Add condition code register names for inline asm (#168…
koachan Nov 19, 2025
4a24947
merge main into amd-staging
ronlieb Nov 19, 2025
fa50a68
[PowerPC] Add custom lowering for SADD overflow for i32 and i64 (#159…
AditiRM Nov 19, 2025
c942ebd
Reapply "[Github] Update PR labeller to v6.0.1 (#167246)"
boomanaiden154 Nov 19, 2025
f7f4135
[LV]: Skip Epilogue scalable VF greater than RemainingIterations. (#1…
hassnaaHamdi Nov 19, 2025
f38cf01
[libclc] Use CLC atomic functions for legacy OpenCL atom/atomic built…
wenju-he Nov 19, 2025
9dc4ebf
[MLIR][XeGPU] Allow create mem desc from 2d memref (#167767)
Jianhui-Li Nov 19, 2025
be1a504
[orc-rt] Simplify Session shutdown. (#168664)
lhames Nov 19, 2025
5bba4fd
[libc] Fix -Wshorten-64-to-32 in fileop_test. (#168451)
vonosmas Nov 19, 2025
ed1c8d7
ELF,test: Test unversioned undefined symbols of index 0 and 1
MaskRay Nov 19, 2025
5109f2a
Exclude from profcheck a vplan test under phase ordering (#168669)
mtrofin Nov 19, 2025
ac68dd5
[RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168…
asb Nov 19, 2025
ec90912
[clang][NVPTX] Add remaining float to fp16 conversions (#167641)
Wolfram70 Nov 19, 2025
669c30c
[MLIR][NVVM] Move docs to correct folder
grypp Nov 19, 2025
58d9e47
[NFCI][bolt][test] Use AT&T syntax explicitly (#167225)
tambry Nov 19, 2025
429e315
[RISCV] Convert -mtune=generic to generic-rv32/rv64 in RISCVSubtarget…
topperc Nov 19, 2025
f8e83c4
[mlir] Use dictionary order to order the pass decl (NFC) (#168648)
linuxlonelyeagle Nov 19, 2025
de9c182
[orc-rt] Initial ORC Runtime design documentation. (#168681)
lhames Nov 19, 2025
fddfc70
[clang-tidy][NFC] Fix order in `list.rst` (#168683)
zeyi2 Nov 19, 2025
711a295
[AMDGPU] Ignore wavefront barrier latency during scheduling DAG mutat…
perlfu Nov 19, 2025
4ab1d06
Reland "[MLIR][NVVM] Add tcgen05.mma MLIR Ops (#164356)" (#168638)
schwarzschild-radius Nov 19, 2025
a2af185
[mlir][tosa] Fix linker failure in build bots introduced by #165581 (…
lhutton1 Nov 19, 2025
907e851
[ORC] Remove now unused EPCDebugObjectRegistrar (NFC) (#167868)
weliveindetail Nov 19, 2025
915e9ad
[clang-tidy] Provide fix-its for casts to void* in google-readability…
ckandeler Nov 19, 2025
0730913
[VPlan] Print debug info for all recipes. (#168454)
fhahn Nov 19, 2025
e38529d
[DAG] Update canCreateUndefOrPoison to handle ISD::VECTOR_COMPRESS (#…
Michael-Chen-NJU Nov 19, 2025
2f6a8a7
[MLIR][NVVM] Add operations and interfaces
grypp Nov 19, 2025
125af56
[AMDGPU][SDAG] Only fold flat offsets if they are inbounds PTRADDs (#…
ritter-x2a Nov 19, 2025
ed7f2a4
[SPARC][NFC] Move clang tests into own subdirectory (#168657)
koachan Nov 19, 2025
1500536
[AllocToken] Fix and clarify -falloc-token-max=0 (#168689)
melver Nov 19, 2025
b42851b
[X86] EltsFromConsecutiveLoads - add recursion depth limiter (#168694)
RKSimon Nov 19, 2025
50791c3
[Clang][X86] allow VPERMILPD/S imm intrinsics to be used in constexpr…
stomfaig Nov 19, 2025
5343dd9
[LifetimeSafety] Detect use-after-return (#165370)
kashika0112 Nov 19, 2025
58e6d02
[AArch64][GlobalISel] Check unmergeSrc is a vector in matchCombineBui…
HolyMolyCowMan Nov 19, 2025
3d3844f
Revert "[AMDGPU] Adding instruction specific features (#167809)"
ronlieb Nov 19, 2025
7b94dd3
[VPLan] Reduce duplication in VPHeaderPHIRecipe::classof. (NFCI)
fhahn Nov 19, 2025
c32c1d0
[Runtimes] Default build must use its own output dirs (#168266)
Meinersbur Nov 19, 2025
d59d11f
merge main into amd-staging
ronlieb Nov 19, 2025
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1,942 changes: 1,130 additions & 812 deletions .github/new-prs-labeler.yml

Large diffs are not rendered by default.

5 changes: 1 addition & 4 deletions .github/workflows/new-prs.yml
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,6 @@ jobs:
# See https://docs.github.com/en/webhooks/webhook-events-and-payloads?actionType=opened#pull_request
# for all the possible values.
if: >-
(github.repository == 'llvm/llvm-project') &&
(github.event.action == 'opened') &&
(github.event.pull_request.author_association != 'COLLABORATOR') &&
(github.event.pull_request.author_association != 'CONTRIBUTOR') &&
Expand Down Expand Up @@ -67,9 +66,7 @@ jobs:
github.event.pull_request.draft == false &&
github.event.pull_request.commits < 10
steps:
- uses: actions/labeler@ac9175f8a1f3625fd0d4fb234536d26811351594 # v4.3.0
- uses: actions/labeler@634933edcd8ababfe52f92936142cc22ac488b1b # v6.0.1
with:
configuration-path: .github/new-prs-labeler.yml
# workaround for https://github.com/actions/labeler/issues/112
sync-labels: ''
repo-token: ${{ secrets.ISSUE_SUBSCRIBER_TOKEN }}
3 changes: 0 additions & 3 deletions .github/workflows/release-binaries.yml
Original file line number Diff line number Diff line change
Expand Up @@ -188,9 +188,6 @@ jobs:
with:
ref: ${{ needs.prepare.outputs.ref }}

- name: Install Ninja
uses: llvm/actions/install-ninja@5dd955034a6742a2e21d82bf165fcb1050ae7b49 # main

- name: Set Build Prefix
id: setup-stage
shell: bash
Expand Down
2 changes: 1 addition & 1 deletion bolt/test/lit.local.cfg
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ if not "linux" in host_triple:
host_triple = host_triple.split("-")[0] + "-unknown-linux-gnu"

common_linker_flags = "-fuse-ld=lld -Wl,--unresolved-symbols=ignore-all -Wl,--build-id=none -pie"
flags = f"--target={host_triple} -fPIE {common_linker_flags}"
flags = f"--target={host_triple} -fPIE {common_linker_flags} -mllvm -x86-asm-syntax=att"

config.substitutions.insert(0, ("%cflags", f"%cflags {flags}"))
config.substitutions.insert(0, ("%cxxflags", f"%cxxflags {flags}"))
6 changes: 6 additions & 0 deletions clang-tools-extra/clang-tidy/google/AvoidCStyleCastsCheck.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -248,6 +248,12 @@ void AvoidCStyleCastsCheck::check(const MatchFinder::MatchResult &Result) {
}
break;
}
if (DestType->isVoidPointerType() && SourceType->isPointerType() &&
!SourceType->getPointeeType()->isPointerType()) {
ReplaceWithNamedCast("reinterpret_cast");
return;
}

[[fallthrough]];
case clang::CK_IntegralCast:
// Convert integral and no-op casts between builtin types and enums to
Expand Down
2 changes: 1 addition & 1 deletion clang-tools-extra/docs/ReleaseNotes.rst
Original file line number Diff line number Diff line change
Expand Up @@ -426,7 +426,7 @@ Changes in existing checks

- Improved :doc:`google-readability-casting
<clang-tidy/checks/google/readability-casting>` check by adding fix-it
notes for downcasts.
notes for downcasts and casts to void pointer.

- Improved :doc:`google-readability-todo
<clang-tidy/checks/google/readability-todo>` check to accept the new TODO
Expand Down
2 changes: 1 addition & 1 deletion clang-tools-extra/docs/clang-tidy/checks/list.rst
Original file line number Diff line number Diff line change
Expand Up @@ -462,9 +462,9 @@ Check aliases
:doc:`cert-mem57-cpp <cert/mem57-cpp>`, :doc:`bugprone-default-operator-new-on-overaligned-type <bugprone/default-operator-new-on-overaligned-type>`,
:doc:`cert-msc24-c <cert/msc24-c>`, :doc:`bugprone-unsafe-functions <bugprone/unsafe-functions>`,
:doc:`cert-msc30-c <cert/msc30-c>`, :doc:`misc-predictable-rand <misc/predictable-rand>`,
:doc:`cert-msc50-cpp <cert/msc50-cpp>`, :doc:`misc-predictable-rand <misc/predictable-rand>`,
:doc:`cert-msc32-c <cert/msc32-c>`, :doc:`bugprone-random-generator-seed <bugprone/random-generator-seed>`,
:doc:`cert-msc33-c <cert/msc33-c>`, :doc:`bugprone-unsafe-functions <bugprone/unsafe-functions>`,
:doc:`cert-msc50-cpp <cert/msc50-cpp>`, :doc:`misc-predictable-rand <misc/predictable-rand>`,
:doc:`cert-msc51-cpp <cert/msc51-cpp>`, :doc:`bugprone-random-generator-seed <bugprone/random-generator-seed>`,
:doc:`cert-msc54-cpp <cert/msc54-cpp>`, :doc:`bugprone-signal-handler <bugprone/signal-handler>`,
:doc:`cert-oop11-cpp <cert/oop11-cpp>`, :doc:`performance-move-constructor-init <performance/move-constructor-init>`,
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,10 @@ void f(int a, double b, const char *cpc, const void *cpv, X *pX) {
// CHECK-MESSAGES: :[[@LINE-1]]:11: warning: {{.*}}; use static_cast {{.*}}
// CHECK-FIXES: Y &rB = static_cast<Y&>(*pX);

void *vp = (void *) pX;
// CHECK-MESSAGES: :[[@LINE-1]]:14: warning: {{.*}}; use reinterpret_cast
// CHECK-FIXES: void *vp = reinterpret_cast<void *>(pX);

const char *pc3 = (const char*)cpv;
// CHECK-MESSAGES: :[[@LINE-1]]:21: warning: {{.*}}; use static_cast [
// CHECK-FIXES: const char *pc3 = static_cast<const char*>(cpv);
Expand Down
6 changes: 3 additions & 3 deletions clang/docs/AllocToken.rst
Original file line number Diff line number Diff line change
Expand Up @@ -52,8 +52,8 @@ change or removal. These may (experimentally) be selected with ``-Xclang
The following command-line options affect generated token IDs:

* ``-falloc-token-max=<N>``
Configures the maximum number of tokens. No max by default (tokens bounded
by ``SIZE_MAX``).
Configures the maximum number of token IDs. By default the number of tokens
is bounded by ``SIZE_MAX``.

Querying Token IDs with ``__builtin_infer_alloc_token``
=======================================================
Expand Down Expand Up @@ -129,7 +129,7 @@ Fast ABI
--------

An alternative ABI can be enabled with ``-fsanitize-alloc-token-fast-abi``,
which encodes the token ID hint in the allocation function name.
which encodes the token ID in the allocation function name.

.. code-block:: c
Expand Down
18 changes: 12 additions & 6 deletions clang/include/clang/Analysis/Analyses/LifetimeSafety/Facts.h
Original file line number Diff line number Diff line change
Expand Up @@ -42,12 +42,12 @@ class Fact {
/// it. Otherwise, the source's loan set is merged into the destination's
/// loan set.
OriginFlow,
/// An origin escapes the function by flowing into the return value.
ReturnOfOrigin,
/// An origin is used (eg. appears as l-value expression like DeclRefExpr).
Use,
/// A marker for a specific point in the code, for testing.
TestPoint,
/// An origin that escapes the function scope (e.g., via return).
OriginEscapes,
};

private:
Expand Down Expand Up @@ -136,16 +136,19 @@ class OriginFlowFact : public Fact {
const OriginManager &OM) const override;
};

class ReturnOfOriginFact : public Fact {
class OriginEscapesFact : public Fact {
OriginID OID;
const Expr *EscapeExpr;

public:
static bool classof(const Fact *F) {
return F->getKind() == Kind::ReturnOfOrigin;
return F->getKind() == Kind::OriginEscapes;
}

ReturnOfOriginFact(OriginID OID) : Fact(Kind::ReturnOfOrigin), OID(OID) {}
OriginID getReturnedOriginID() const { return OID; }
OriginEscapesFact(OriginID OID, const Expr *EscapeExpr)
: Fact(Kind::OriginEscapes), OID(OID), EscapeExpr(EscapeExpr) {}
OriginID getEscapedOriginID() const { return OID; }
const Expr *getEscapeExpr() const { return EscapeExpr; };
void dump(llvm::raw_ostream &OS, const LoanManager &,
const OriginManager &OM) const override;
};
Expand Down Expand Up @@ -225,6 +228,9 @@ class FactManager {
/// user-defined locations in the code.
/// \note This is intended for testing only.
llvm::StringMap<ProgramPoint> getTestPoints() const;
/// Retrieves all the facts in the block containing Program Point P.
/// \note This is intended for testing only.
llvm::ArrayRef<const Fact *> getBlockContaining(ProgramPoint P) const;

unsigned getNumFacts() const { return NextFactID.Value; }

Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -94,6 +94,10 @@ class FactsGenerator : public ConstStmtVisitor<FactsGenerator> {
FactManager &FactMgr;
AnalysisDeclContext &AC;
llvm::SmallVector<Fact *> CurrentBlockFacts;
// Collect origins that escape the function in this block (OriginEscapesFact),
// appended at the end of CurrentBlockFacts to ensure they appear after
// ExpireFact entries.
llvm::SmallVector<Fact *> EscapesInCurrentBlock;
// To distinguish between reads and writes for use-after-free checks, this map
// stores the `UseFact` for each `DeclRefExpr`. We initially identify all
// `DeclRefExpr`s as "read" uses. When an assignment is processed, the use
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,11 @@ class LifetimeSafetyReporter {
virtual void reportUseAfterFree(const Expr *IssueExpr, const Expr *UseExpr,
SourceLocation FreeLoc,
Confidence Confidence) {}

virtual void reportUseAfterReturn(const Expr *IssueExpr,
const Expr *EscapeExpr,
SourceLocation ExpiryLoc,
Confidence Confidence) {}
};

/// The main entry point for the analysis.
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,9 @@

namespace clang::lifetimes::internal {

using CausingFactType =
::llvm::PointerUnion<const UseFact *, const OriginEscapesFact *>;

enum class LivenessKind : uint8_t {
Dead, // Not alive
Maybe, // Live on some path but not all paths (may-be-live)
Expand All @@ -43,7 +46,7 @@ struct LivenessInfo {
/// multiple uses along different paths, this will point to the use appearing
/// earlier in the translation unit.
/// This is 'null' when the origin is not live.
const UseFact *CausingUseFact;
CausingFactType CausingFact;

/// The kind of liveness of the origin.
/// `Must`: The origin is live on all control-flow paths from the current
Expand All @@ -56,17 +59,16 @@ struct LivenessInfo {
/// while `Maybe`-be-alive suggests a potential one on some paths.
LivenessKind Kind;

LivenessInfo() : CausingUseFact(nullptr), Kind(LivenessKind::Dead) {}
LivenessInfo(const UseFact *UF, LivenessKind K)
: CausingUseFact(UF), Kind(K) {}
LivenessInfo() : CausingFact(nullptr), Kind(LivenessKind::Dead) {}
LivenessInfo(CausingFactType CF, LivenessKind K) : CausingFact(CF), Kind(K) {}

bool operator==(const LivenessInfo &Other) const {
return CausingUseFact == Other.CausingUseFact && Kind == Other.Kind;
return CausingFact == Other.CausingFact && Kind == Other.Kind;
}
bool operator!=(const LivenessInfo &Other) const { return !(*this == Other); }

void Profile(llvm::FoldingSetNodeID &IDBuilder) const {
IDBuilder.AddPointer(CausingUseFact);
IDBuilder.AddPointer(CausingFact.getOpaqueValue());
IDBuilder.Add(Kind);
}
};
Expand Down
21 changes: 21 additions & 0 deletions clang/include/clang/Basic/BuiltinsNVPTX.td
Original file line number Diff line number Diff line change
Expand Up @@ -579,6 +579,10 @@ def __nvvm_ff2bf16x2_rn : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float)
def __nvvm_ff2bf16x2_rn_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float)", SM_80, PTX70>;
def __nvvm_ff2bf16x2_rz : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float)", SM_80, PTX70>;
def __nvvm_ff2bf16x2_rz_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float)", SM_80, PTX70>;
def __nvvm_ff2bf16x2_rn_satfinite : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float)", SM_80, PTX81>;
def __nvvm_ff2bf16x2_rn_relu_satfinite : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float)", SM_80, PTX81>;
def __nvvm_ff2bf16x2_rz_satfinite : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float)", SM_80, PTX81>;
def __nvvm_ff2bf16x2_rz_relu_satfinite : NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float)", SM_80, PTX81>;
def __nvvm_ff2bf16x2_rs :
NVPTXBuiltinSMAndPTX<"_Vector<2, __bf16>(float, float, uint32_t)",
SM<"100a", [SM_103a]>, PTX87>;
Expand All @@ -596,6 +600,10 @@ def __nvvm_ff2f16x2_rn : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float)"
def __nvvm_ff2f16x2_rn_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float)", SM_80, PTX70>;
def __nvvm_ff2f16x2_rz : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float)", SM_80, PTX70>;
def __nvvm_ff2f16x2_rz_relu : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float)", SM_80, PTX70>;
def __nvvm_ff2f16x2_rn_satfinite : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float)", SM_80, PTX81>;
def __nvvm_ff2f16x2_rn_relu_satfinite : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float)", SM_80, PTX81>;
def __nvvm_ff2f16x2_rz_satfinite : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float)", SM_80, PTX81>;
def __nvvm_ff2f16x2_rz_relu_satfinite : NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float)", SM_80, PTX81>;
def __nvvm_ff2f16x2_rs :
NVPTXBuiltinSMAndPTX<"_Vector<2, __fp16>(float, float, uint32_t)",
SM<"100a", [SM_103a]>, PTX87>;
Expand All @@ -613,6 +621,19 @@ def __nvvm_f2bf16_rn : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX70>;
def __nvvm_f2bf16_rn_relu : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX70>;
def __nvvm_f2bf16_rz : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX70>;
def __nvvm_f2bf16_rz_relu : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX70>;
def __nvvm_f2bf16_rn_satfinite : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX81>;
def __nvvm_f2bf16_rn_relu_satfinite : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX81>;
def __nvvm_f2bf16_rz_satfinite : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX81>;
def __nvvm_f2bf16_rz_relu_satfinite : NVPTXBuiltinSMAndPTX<"__bf16(float)", SM_80, PTX81>;

def __nvvm_f2f16_rn : NVPTXBuiltinSMAndPTX<"__fp16(float)", SM_80, PTX70>;
def __nvvm_f2f16_rn_relu : NVPTXBuiltinSMAndPTX<"__fp16(float)", SM_80, PTX70>;
def __nvvm_f2f16_rz : NVPTXBuiltinSMAndPTX<"__fp16(float)", SM_80, PTX70>;
def __nvvm_f2f16_rz_relu : NVPTXBuiltinSMAndPTX<"__fp16(float)", SM_80, PTX70>;
def __nvvm_f2f16_rn_satfinite : NVPTXBuiltinSMAndPTX<"__fp16(float)", SM_80, PTX81>;
def __nvvm_f2f16_rn_relu_satfinite : NVPTXBuiltinSMAndPTX<"__fp16(float)", SM_80, PTX81>;
def __nvvm_f2f16_rz_satfinite : NVPTXBuiltinSMAndPTX<"__fp16(float)", SM_80, PTX81>;
def __nvvm_f2f16_rz_relu_satfinite : NVPTXBuiltinSMAndPTX<"__fp16(float)", SM_80, PTX81>;

def __nvvm_f2tf32_rna : NVPTXBuiltinSMAndPTX<"int32_t(float)", SM_80, PTX70>;
def __nvvm_f2tf32_rna_satfinite : NVPTXBuiltinSMAndPTX<"int32_t(float)", SM_80, PTX81>;
Expand Down
12 changes: 7 additions & 5 deletions clang/include/clang/Basic/BuiltinsX86.td
Original file line number Diff line number Diff line change
Expand Up @@ -512,7 +512,7 @@ let Features = "avx", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in
def vperm2f128_si256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Constant int)">;
}

let Features = "avx", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in {
let Features = "avx", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<128>] in {
def vpermilpd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Constant int)">;
def vpermilps : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Constant int)">;
}
Expand All @@ -528,6 +528,8 @@ let Features = "avx", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWid
def vinsertf128_pd256 : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Vector<2, double>, _Constant int)">;
def vinsertf128_ps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<4, float>, _Constant int)">;
def vinsertf128_si256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<4, int>, _Constant int)">;
def vpermilpd256 : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Constant int)">;
def vpermilps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Constant int)">;

foreach Op = ["hadd", "hsub"] in {
def Op#pd256 : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Vector<4, double>)">;
Expand All @@ -536,8 +538,6 @@ let Features = "avx", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWid
}

let Features = "avx", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in {
def vpermilpd256 : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Constant int)">;
def vpermilps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Constant int)">;
def sqrtpd256 : X86Builtin<"_Vector<4, double>(_Vector<4, double>)">;
def sqrtps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>)">;
def rsqrtps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>)">;
Expand Down Expand Up @@ -2375,10 +2375,12 @@ let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<128>
def vcvttss2si32 : X86Builtin<"int(_Vector<4, float>, _Constant int)">;
def vcvttss2usi32 : X86Builtin<"unsigned int(_Vector<4, float>, _Constant int)">;
}

let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in {
def vpermilpd512 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Constant int)">;
def vpermilps512 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Constant int)">;
}

let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in {
def vpermilvarpd512 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, long long int>)">;
def vpermilvarps512 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, int>)">;
}
Expand Down
11 changes: 11 additions & 0 deletions clang/include/clang/Basic/DiagnosticSemaKinds.td
Original file line number Diff line number Diff line change
Expand Up @@ -10740,8 +10740,19 @@ def warn_lifetime_safety_loan_expires_permissive : Warning<
def warn_lifetime_safety_loan_expires_strict : Warning<
"object whose reference is captured may not live long enough">,
InGroup<LifetimeSafetyStrict>, DefaultIgnore;

def warn_lifetime_safety_return_stack_addr_permissive
: Warning<"address of stack memory is returned later">,
InGroup<LifetimeSafetyPermissive>,
DefaultIgnore;
def warn_lifetime_safety_return_stack_addr_strict
: Warning<"address of stack memory may be returned later">,
InGroup<LifetimeSafetyStrict>,
DefaultIgnore;

def note_lifetime_safety_used_here : Note<"later used here">;
def note_lifetime_safety_destroyed_here : Note<"destroyed here">;
def note_lifetime_safety_returned_here : Note<"returned here">;

// For non-floating point, expressions of the form x == x or x != x
// should result in a warning, since these always evaluate to a constant.
Expand Down
4 changes: 2 additions & 2 deletions clang/include/clang/Basic/LangOptions.h
Original file line number Diff line number Diff line change
Expand Up @@ -566,8 +566,8 @@ class LangOptions : public LangOptionsBase {
bool AtomicFineGrainedMemory = false;
bool AtomicIgnoreDenormalMode = false;

/// Maximum number of allocation tokens (0 = no max), nullopt if none set (use
/// target default).
/// Maximum number of allocation tokens (0 = target SIZE_MAX), nullopt if none
/// set (use target SIZE_MAX).
std::optional<uint64_t> AllocTokenMax;

/// The allocation token mode.
Expand Down
2 changes: 1 addition & 1 deletion clang/include/clang/Options/Options.td
Original file line number Diff line number Diff line change
Expand Up @@ -2764,7 +2764,7 @@ defm sanitize_alloc_token_extended : BoolOption<"f", "sanitize-alloc-token-exten
def falloc_token_max_EQ : Joined<["-"], "falloc-token-max=">,
Group<f_Group>, Visibility<[ClangOption, CC1Option]>,
MetaVarName<"<N>">,
HelpText<"Limit to maximum N allocation tokens (0 = no max)">;
HelpText<"Limit to maximum N allocation tokens (0 = target SIZE_MAX)">;

def falloc_token_mode_EQ : Joined<["-"], "falloc-token-mode=">,
Group<f_Group>, Visibility<[CC1Option]>,
Expand Down
22 changes: 21 additions & 1 deletion clang/lib/AST/ByteCode/InterpBuiltin.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1317,8 +1317,9 @@ static bool interp__builtin_infer_alloc_token(InterpState &S, CodePtr OpPC,
uint64_t BitWidth = ASTCtx.getTypeSize(ASTCtx.getSizeType());
auto Mode =
ASTCtx.getLangOpts().AllocTokenMode.value_or(llvm::DefaultAllocTokenMode);
auto MaxTokensOpt = ASTCtx.getLangOpts().AllocTokenMax;
uint64_t MaxTokens =
ASTCtx.getLangOpts().AllocTokenMax.value_or(~0ULL >> (64 - BitWidth));
MaxTokensOpt.value_or(0) ? *MaxTokensOpt : (~0ULL >> (64 - BitWidth));

// We do not read any of the arguments; discard them.
for (int I = Call->getNumArgs() - 1; I >= 0; --I)
Expand Down Expand Up @@ -4619,6 +4620,9 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
case X86::BI__builtin_ia32_pshufd:
case X86::BI__builtin_ia32_pshufd256:
case X86::BI__builtin_ia32_pshufd512:
case X86::BI__builtin_ia32_vpermilps:
case X86::BI__builtin_ia32_vpermilps256:
case X86::BI__builtin_ia32_vpermilps512:
return interp__builtin_ia32_shuffle_generic(
S, OpPC, Call, [](unsigned DstIdx, unsigned ShuffleMask) {
unsigned LaneBase = (DstIdx / 4) * 4;
Expand All @@ -4627,6 +4631,22 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
return std::make_pair(0, static_cast<int>(LaneBase + Sel));
});

case X86::BI__builtin_ia32_vpermilpd:
case X86::BI__builtin_ia32_vpermilpd256:
case X86::BI__builtin_ia32_vpermilpd512:
return interp__builtin_ia32_shuffle_generic(
S, OpPC, Call, [](unsigned DstIdx, unsigned Control) {
unsigned NumElemPerLane = 2;
unsigned BitsPerElem = 1;
unsigned MaskBits = 8;
unsigned IndexMask = 0x1;
unsigned Lane = DstIdx / NumElemPerLane;
unsigned LaneOffset = Lane * NumElemPerLane;
unsigned BitIndex = (DstIdx * BitsPerElem) % MaskBits;
unsigned Index = (Control >> BitIndex) & IndexMask;
return std::make_pair(0, static_cast<int>(LaneOffset + Index));
});

case X86::BI__builtin_ia32_kandqi:
case X86::BI__builtin_ia32_kandhi:
case X86::BI__builtin_ia32_kandsi:
Expand Down
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