L1 Cache Design in Verilog (Direct-Mapped, 4-Way, Fully-Associative)

Course: EE 275 – Advanced Computer Architecture
Summary: Verilog implementation of multiple L1 data cache architectures, evaluated using matrix-style workloads to compare locality, associativity, and replacement policies.

Implemented Cache Architectures

Direct-Mapped Cache

• l1_cache_dm_8kb_simple.v

4-Way Set-Associative Cache

• l1_cache_4way_random.v
• l1_cache_4way_lru.v

Fully-Associative Cache

• l1_cache_fully_assoc_random.v
• l1_cache_fully_assoc_lru.v

Supporting Modules

• addr_alu.v
• alu_gates.v
• alu_gates_64.v
• eq_alu.v
• regs_and_counters.v

Testbenches

• top_matrix_final_tb.v
• top_matrix_4way_tb.v
• top_matrix_fully_assoc_tb.v
• top_matrix_fully_assoc_lru_tb.v
• top_matrix_lru_tb.v
• top_matrix_phases_simple_tb.v

Simulation Outputs

• Simulation binaries: sim, sim_FINAL, sim_DEBUG, sim_REALLY_FIXED, sim_fully_assoc, sim_fully_assoc_random, sim_fully_assoc_lru, sim_part_b, sim_part_c
• Logs: results_part_b.log, results_part_c.log

These contain the measured cache miss counts and performance metrics.

How to Run (example with Icarus Verilog)

iverilog -o sim top_matrix_final_tb.v l1_cache_4way_lru.v alu_gates.v regs_and_counters.v ...
./sim

Project Goals

Compare direct-mapped vs set-associative vs fully associative L1 designs

Study LRU vs random replacement policies

Observe locality effects with matrix-style memory access patterns

Measure cache hits, misses, and memory accesses