Separate instruction and data memories

[Rishu31]

Hi, is it possible to configure Vex II to have separate instruction and data memories?
If yes, how to do it?

[Dolu1990]

In what sense do you mean it ? to have memory space unrelated ?
probablly you would need to tune the

VexiiRiscv/src/main/scala/vexiiriscv/memory/StaticTranslationPlugin.scala

Line 18 in 4d27d44

class StaticTranslationPlugin(var physicalWidth: Int) extends FiberPlugin with AddressTranslationService {

[Jzjerry]

I think in Micro Soc you can just create 2 different RAMs and place them on different addresses, then rewrite the linker script for separate .text and .data .

[Rishu31]

Oh.. so you mean 2 memory plugins? And the internal logistics of when to access the data memory or instr memory would be taken care of while generating Verilog?