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v0.1.0

General Idea

Implement a simple 5 stage RISC-V Non pipelined architecture and test it.

Features to be implemented

• Instruction Decode;
• Execute Stage;
• Memory Access;
• Write back;

Done

• Instruction Fetch;

Technical Details

Instruction Memory

Instruction memory will consist of a ROM BRAM (Read only memory Block RAM), for the time being with a width of 32 bits (instruction size, RISC-V like) and a depth of 4096 instructions. The block memory is defined as a single port ROM, that's because we are only interested in reading the hardcoded RISC-V instructions inside of it. The BRAM will have an enable pin and a synchronous reset pin (will only work when memory is enabled). The IP will have an embedded output register where the Instruction to be decoded is saved before the instruction decode stage. The input address is 32 bit wide to ease RISC-V jump instructions. For this time the load_en for the instruction memory will be hard-wired to "1".

Clock

• Clock is now set at 50 MHz, let's try if it works.

Instruction Fetch Stage

The entire instruction fetch stage is executed in one clock cycle. Here is the flow of operations:

• If LOAD_EN is active, incoming PC from upper stages is loaded into the PC register (beware, this happens 1 clock cycle before the start of the instruction fetch)
• Rising edge of the clock arrives
• BRAM Instruction Memory fetches instruction reading PC if LOAD_EN_MEM is active. A synchronous RST may reset the Instruction Memory
• In the meantime PC + 4 is computed and saved in NPC (Next Program Counter)
• BRAM will save Instruction in internal IR (instruction register) before the arrival of the next clock pulse

Instruction Decode