Merge remote-tracking branch 'origin/master' into HEAD

Author: oharboe

flow/MODULE.bazel

@@ -15,17 +15,6 @@ git_override(
     remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git",
 )
 
-# Read: https://github.com/The-OpenROAD-Project/bazel-orfs?tab=readme-ov-file#usage
-#
-# TL;DR
-#
-# 1. uncomment below
-# 2. comment git_override() above
-#
-#local_path_override(
-#   module_name = "bazel-orfs", path = "../bazel-orfs"
-#)
-
 bazel_dep(name = "rules_python", version = "0.31.0")
 
 python = use_extension("@rules_python//python/extensions:python.bzl", "python")

flow/designs/sky130hd/microwatt/rules-base.json

@@ -40,7 +40,7 @@
         "compare": "<="
     },
     "detailedroute__antenna__violating__nets": {
-        "value": 0,
+        "value": 1,
         "compare": "<="
     },
     "detailedroute__antenna_diodes_count": {

flow/platforms/ihp-sg13g2/config.mk

@@ -139,3 +139,11 @@ export CDL_FILE ?= $(PLATFORM_DIR)/cdl/sg13g2_stdcell.cdl
 
 #Temporary: skip post-DRT repair antennas
 export SKIP_ANTENNA_REPAIR_POST_DRT = 1
+
+# ---------------------------------------------------------
+#  Final
+# ---------------------------------------------------------
+
+# SRAM macros have empty placeholder cells included. Just ignore them to not
+# thrown an error.
+export GDS_ALLOW_EMPTY = RM_IHPSG13_1P_BITKIT_16x2_(CORNER|EDGE_TB|LE_con_corner|LE_con_edge_lr|LE_con_tap_lr|POWER_ramtap|TAP|TAP_LR)

flow/scripts/open.tcl

@@ -41,7 +41,7 @@ proc read_timing {input_file} {
   if {$design_stage >= 6 && [file exist $::env(RESULTS_DIR)/6_final.spef]} {
     log_cmd read_spef $::env(RESULTS_DIR)/6_final.spef
   } elseif {$design_stage >= 5} {
-    if { [grt::have_routes] } {
+    if { [log_cmd grt::have_routes] } {
       log_cmd estimate_parasitics -global_routing
     } else {
       puts "No global routing results available, skipping estimate_parasitics"
@@ -51,10 +51,8 @@ proc read_timing {input_file} {
     log_cmd estimate_parasitics -placement
   }
 
-  puts -nonewline "Populating timing paths..."
   # Warm up OpenSTA, so clicking on timing related buttons reacts faster
-  set _tmp [find_timing_paths]
-  puts "OK"
+  set _tmp [log_cmd find_timing_paths]
 }
 
 if {[ord::openroad_gui_compiled]} {

flow/scripts/util.tcl

@@ -3,13 +3,14 @@ proc log_cmd {cmd args} {
   set log_cmd "$cmd[join [lmap arg $args {format " %s" [expr {[string match {* *} $arg] ? "\"$arg\"" : "$arg"}]}] ""]"
   puts $log_cmd
   set start [clock seconds]
-  $cmd {*}$args
+  set result [uplevel 1 [list $cmd {*}$args]]
   set time [expr {[clock seconds] - $start}]
   if {$time >= 5} {
     # Ideally we'd use a single line, but the command can output text
     # and we don't want to mix it with the log, so output the time it took afterwards.
     puts "Took $time seconds: $log_cmd"
   }
+  return $result
 }
 
 proc fast_route {} {

flow/scripts/write_ref_sdc.tcl

@@ -25,7 +25,7 @@ if { [llength $clks] == 0 } {
       create_clock -name $clk_name -period $ref_period $sources
       # Undo the set_propagated_clock so SDC at beginning of flow uses ideal clocks.
       unset_propagated_clock [all_clocks]
-      write_sdc -no_timestamp [file join $env(RESULTS_DIR) "updated_clks.sdc"]
+      write_sdc -no_timestamp [file join $::env(RESULTS_DIR) "updated_clks.sdc"]
       # Reset
       create_clock -name $clk_name -period $period $sources
       set_propagated_clock [all_clocks]

flow/util/def2stream.py

@@ -20,43 +20,40 @@
 for i in main_layout.each_cell():
     print("[INFO] '{0}'".format(i.name))
 
-print("[INFO] Reading DEF ...")
 main_layout.read(in_def, layoutOptions)
 
 # Clear cells
 top_cell_index = main_layout.cell(design_name).cell_index()
 
 # remove orphan cell BUT preserve cell with VIA_
 #  - KLayout is prepending VIA_ when reading DEF that instantiates LEF's via
-print("[INFO] Clearing cells...")
 for i in main_layout.each_cell():
     if i.cell_index() != top_cell_index:
         if not i.name.startswith("VIA_") and not i.name.endswith("_DEF_FILL"):
             i.clear()
 
 # Load in the gds to merge
-print("[INFO] Merging GDS/OAS files...")
 for fil in in_files.split():
     print("\t{0}".format(fil))
     main_layout.read(fil)
 
 # Copy the top level only to a new layout
-print("[INFO] Copying toplevel cell '{0}'".format(design_name))
 top_only_layout = pya.Layout()
 top_only_layout.dbu = main_layout.dbu
 top = top_only_layout.create_cell(design_name)
 top.copy_tree(main_layout.cell(design_name))
 
-print("[INFO] Checking for missing cell from GDS/OAS...")
 missing_cell = False
-regex = None
-if "GDS_ALLOW_EMPTY" in os.environ:
-    print("[INFO] Found GDS_ALLOW_EMPTY variable.")
-    regex = os.getenv("GDS_ALLOW_EMPTY")
+allow_empty = os.environ.get("GDS_ALLOW_EMPTY", "")
+regex = re.compile(allow_empty) if allow_empty else None
+
+if allow_empty:
+    print(f"[INFO] GDS_ALLOW_EMPTY={allow_empty}")
+
 for i in top_only_layout.each_cell():
     if i.is_empty():
         missing_cell = True
-        if regex is not None and re.match(regex, i.name):
+        if regex is not None and regex.match(i.name):
             print(
                 "[WARNING] LEF Cell '{0}' ignored. Matches GDS_ALLOW_EMPTY.".format(
                     i.name
@@ -72,7 +69,6 @@
 if not missing_cell:
     print("[INFO] All LEF cells have matching GDS/OAS cells")
 
-print("[INFO] Checking for orphan cell in the final layout...")
 orphan_cell = False
 for i in top_only_layout.each_cell():
     if i.name != design_name and i.parent_cells() == 0:
@@ -81,14 +77,12 @@
         errors += 1
 
 if not orphan_cell:
-    print("[INFO] No orphan cells")
+    print("[INFO] No orphan cells in the final layout")
 
 
 if seal_file:
     top_cell = top_only_layout.top_cell()
 
-    print("[INFO] Reading seal GDS/OAS file...")
-    print("\t{0}".format(seal_file))
     top_only_layout.read(seal_file)
 
     for cell in top_only_layout.top_cells():
@@ -101,7 +95,6 @@
             top.insert(pya.CellInstArray(cell.cell_index(), pya.Trans()))
 
 # Write out the GDS
-print("[INFO] Writing out GDS/OAS '{0}'".format(out_file))
 top_only_layout.write(out_file)
 
 sys.exit(errors)