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flow: Move pre-place buffering from abc to OR floorplan
Signed-off-by: Martin Povišer <povik@cutebit.org>
1 parent a8a56ba commit ba891a1

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19 files changed

+43
-48
lines changed

19 files changed

+43
-48
lines changed

‎flow/designs/asap7/minimal/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,5 +19,5 @@ export SKIP_REPORT_METRICS = 1
1919

2020
# Faster build, remove these in your own config.mk
2121
export SKIP_CTS_REPAIR_TIMING = 1
22-
export REMOVE_ABC_BUFFERS = 1
22+
export FLOORPLAN_BUFFERING = 0
2323
export SKIP_INCREMENTAL_REPAIR = 1

‎flow/designs/gf12/ariane/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,4 +36,4 @@ else
3636
export DESIGN_TYPE = CELL_NODEN
3737
endif
3838

39-
export REMOVE_ABC_BUFFERS = 1
39+
export FLOORPLAN_BUFFERING = 0

‎flow/designs/gf12/ariane133/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,4 +30,4 @@ else
3030
export DESIGN_TYPE = CELL_NODEN
3131
endif
3232

33-
export REMOVE_ABC_BUFFERS = 1
33+
export FLOORPLAN_BUFFERING = 0

‎flow/designs/gf12/swerv_wrapper/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,4 +42,4 @@ else
4242
export DESIGN_TYPE = CELL_NODEN
4343
endif
4444

45-
export REMOVE_ABC_BUFFERS = 1
45+
export FLOORPLAN_BUFFERING = 0

‎flow/designs/ihp-sg13g2/aes/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,4 +13,4 @@ export TNS_END_PERCENT = 100
1313

1414
export USE_FILL = 1
1515

16-
export REMOVE_ABC_BUFFERS = 1
16+
export FLOORPLAN_BUFFERING = 0

‎flow/designs/ihp-sg13g2/jpeg/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,5 +10,5 @@ export CORE_UTILIZATION = 55
1010
export PLACE_DENSITY_LB_ADDON = 0.20
1111
export TNS_END_PERCENT = 100
1212

13-
export REMOVE_ABC_BUFFERS = 1
13+
export FLOORPLAN_BUFFERING = 0
1414

‎flow/designs/sky130hd/aes/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ export TNS_END_PERCENT = 100
1616

1717
export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
1818

19-
export REMOVE_ABC_BUFFERS = 1
19+
export FLOORPLAN_BUFFERING = 0
2020

2121
export CTS_CLUSTER_SIZE = 20
2222
export CTS_CLUSTER_DIAMETER = 50

‎flow/designs/sky130hd/ibex/BUILD.bazel

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ orfs_flow(
77
"CORE_UTILIZATION": "45",
88
"PLACE_DENSITY_LB_ADDON": "0.2",
99
"TNS_END_PERCENT": "100",
10-
"REMOVE_ABC_BUFFERS": "1",
10+
"FLOORPLAN_BUFFERING": "0",
1111
},
1212
pdk = "@docker_orfs//:sky130hd",
1313
sources = {

‎flow/designs/sky130hd/ibex/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ export TNS_END_PERCENT = 100
5151

5252
export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
5353

54-
export REMOVE_ABC_BUFFERS = 1
54+
export FLOORPLAN_BUFFERING = 0
5555

5656
export CTS_CLUSTER_SIZE = 20
5757
export CTS_CLUSTER_DIAMETER = 50

‎flow/designs/sky130hd/jpeg/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,4 +12,4 @@ export TNS_END_PERCENT = 100
1212

1313
export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
1414

15-
export REMOVE_ABC_BUFFERS = 1
15+
export FLOORPLAN_BUFFERING = 0

‎flow/designs/sky130hd/riscv32i/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,4 +8,4 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.
88
export CORE_UTILIZATION = 45
99
export PLACE_DENSITY_LB_ADDON = 0.2
1010

11-
export REMOVE_ABC_BUFFERS = 1
11+
export FLOORPLAN_BUFFERING = 0

‎flow/designs/sky130hs/aes/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ export CORE_MARGIN = 2
1212
export PLACE_DENSITY_LB_ADDON = 0.25
1313
export TNS_END_PERCENT = 100
1414

15-
export REMOVE_ABC_BUFFERS = 1
15+
export FLOORPLAN_BUFFERING = 0
1616

1717
export CTS_CLUSTER_SIZE = 10
1818
export CTS_CLUSTER_DIAMETER = 50

‎flow/designs/sky130hs/ibex/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,4 +45,4 @@ export CORE_UTILIZATION = 45
4545
export PLACE_DENSITY_LB_ADDON = 0.2
4646
export TNS_END_PERCENT = 100
4747

48-
export REMOVE_ABC_BUFFERS = 1
48+
export FLOORPLAN_BUFFERING = 0

‎flow/designs/sky130hs/riscv32i/config.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,4 +13,4 @@ export TNS_END_PERCENT = 100
1313

1414
export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
1515

16-
export REMOVE_ABC_BUFFERS = 1
16+
export FLOORPLAN_BUFFERING = 0

‎flow/scripts/abc_speed.script

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -28,8 +28,3 @@
2828
&synch2
2929
&nf
3030
&put
31-
buffer -c
32-
topo
33-
stime -c
34-
upsize -c
35-
dnsize -c

‎flow/scripts/floorplan.tcl

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,26 @@ check_setup
4040
set num_instances [llength [get_cells -hier *]]
4141
puts "number instances in verilog is $num_instances"
4242

43+
# Strip all incoming buffers
44+
remove_buffers
45+
46+
set_dont_use $::env(DONT_USE_CELLS)
47+
48+
# Do not buffer chip-level designs
49+
# by default, IO ports will be buffered
50+
# to not buffer IO ports, set environment variable
51+
# DONT_BUFFER_PORT = 1
52+
if { ![env_var_exists_and_non_empty FOOTPRINT] } {
53+
if { ![env_var_equals DONT_BUFFER_PORTS 1] } {
54+
puts "Perform port buffering..."
55+
buffer_ports
56+
}
57+
}
58+
59+
if {[env_var_equals FLOORPLAN_BUFFERING 1]} {
60+
repair_design_helper -pre_placement
61+
}
62+
4363
set additional_args ""
4464
append_env_var additional_args ADDITIONAL_SITES -additional_sites 1
4565

@@ -103,13 +123,6 @@ if {[env_var_exists_and_non_empty FOOTPRINT_TCL]} {
103123
log_cmd source $::env(FOOTPRINT_TCL)
104124
}
105125

106-
if { [env_var_equals REMOVE_ABC_BUFFERS 1] } {
107-
# remove buffers inserted by yosys/abc
108-
remove_buffers
109-
} else {
110-
repair_timing_helper 0
111-
}
112-
113126
##### Restructure for timing #########
114127
if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } {
115128
repair_design_helper

‎flow/scripts/resize.tcl

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -10,17 +10,6 @@ set pin_count_before [sta::network_leaf_pin_count]
1010

1111
set_dont_use $::env(DONT_USE_CELLS)
1212

13-
# Do not buffer chip-level designs
14-
# by default, IO ports will be buffered
15-
# to not buffer IO ports, set environment variable
16-
# DONT_BUFFER_PORT = 1
17-
if { ![env_var_exists_and_non_empty FOOTPRINT] } {
18-
if { ![env_var_equals DONT_BUFFER_PORTS 1] } {
19-
puts "Perform port buffering..."
20-
buffer_ports
21-
}
22-
}
23-
2413
repair_design_helper
2514

2615
if { [env_var_exists_and_non_empty TIE_SEPARATION] } {

‎flow/scripts/util.tcl

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -40,14 +40,14 @@ proc repair_timing_helper { {hold_margin 1} } {
4040
log_cmd repair_timing {*}$additional_args
4141
}
4242

43-
proc repair_design_helper {} {
43+
proc repair_design_helper { {extra_args ""} } {
4444
puts "Perform buffer insertion and gate resizing..."
4545

46-
set additional_args "-verbose"
47-
append_env_var additional_args CAP_MARGIN -cap_margin 1
48-
append_env_var additional_args SLEW_MARGIN -slew_margin 1
49-
append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
50-
log_cmd repair_design {*}$additional_args
46+
set args "-verbose"
47+
append_env_var args CAP_MARGIN -cap_margin 1
48+
append_env_var args SLEW_MARGIN -slew_margin 1
49+
append_env_var args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
50+
log_cmd repair_design {*}$args {*}$extra_args
5151
}
5252

5353
proc recover_power_helper {} {

‎flow/scripts/variables.yaml

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -254,14 +254,12 @@ FLOORPLAN_DEF:
254254
stages:
255255
- floorplan
256256
- place
257-
REMOVE_ABC_BUFFERS:
257+
FLOORPLAN_BUFFERING:
258258
description: >
259-
Remove abc buffers from the netlist. If timing repair in floorplanning is
260-
taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early
261-
instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.
259+
Perform a pre-placement buffering round at the floorplan stage.
262260
stages:
263261
- floorplan
264-
deprecated: 1
262+
default: 1
265263
PLACE_SITE:
266264
description: |
267265
Placement site for core cells defined in the technology LEF file.

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