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flow: Move pre-place buffering from abc to OR floorplan #3101

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9d56d8e
flow: Move pre-place buffering from abc to OR floorplan
povik Apr 23, 2025
88012a0
Merge branch 'master' into floorplan-buffering
povik May 14, 2025
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4 changes: 2 additions & 2 deletions docs/user/FlowVariables.md
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Expand Up @@ -95,6 +95,7 @@ configuration file.
| <a name="FASTROUTE_TCL"></a>FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| | |
| <a name="FILL_CELLS"></a>FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| | |
| <a name="FILL_CONFIG"></a>FILL_CONFIG| JSON rule file for metal fill during chip finishing.| | |
| <a name="FLOORPLAN_BUFFERING"></a>FLOORPLAN_BUFFERING| Perform a pre-placement buffering round at the floorplan stage.| 1| |
| <a name="FLOORPLAN_DEF"></a>FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| | |
| <a name="FLOW_VARIANT"></a>FLOW_VARIANT| Flow variant to use, used in the flow variant directory name.| base| |
| <a name="GDS_ALLOW_EMPTY"></a>GDS_ALLOW_EMPTY| Regular expression of module names of macros that have no .gds file| | |
Expand Down Expand Up @@ -138,7 +139,6 @@ configuration file.
| <a name="PWR_NETS_VOLTAGES"></a>PWR_NETS_VOLTAGES| Used for IR Drop calculation.| | |
| <a name="RCX_RULES"></a>RCX_RULES| RC Extraction rules file path.| | |
| <a name="RECOVER_POWER"></a>RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0| |
| <a name="REMOVE_ABC_BUFFERS"></a>REMOVE_ABC_BUFFERS| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.| | yes|
| <a name="REMOVE_CELLS_FOR_EQY"></a>REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| | |
| <a name="REPAIR_PDN_VIA_LAYER"></a>REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| | |
| <a name="REPORT_CLOCK_SKEW"></a>REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1| |
Expand Down Expand Up @@ -239,6 +239,7 @@ configuration file.
- [CORE_MARGIN](#CORE_MARGIN)
- [CORE_UTILIZATION](#CORE_UTILIZATION)
- [DIE_AREA](#DIE_AREA)
- [FLOORPLAN_BUFFERING](#FLOORPLAN_BUFFERING)
- [FLOORPLAN_DEF](#FLOORPLAN_DEF)
- [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN)
- [IO_CONSTRAINTS](#IO_CONSTRAINTS)
Expand All @@ -255,7 +256,6 @@ configuration file.
- [PLACE_DENSITY](#PLACE_DENSITY)
- [PLACE_DENSITY_LB_ADDON](#PLACE_DENSITY_LB_ADDON)
- [PLACE_SITE](#PLACE_SITE)
- [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS)
- [RESYNTH_AREA_RECOVER](#RESYNTH_AREA_RECOVER)
- [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER)
- [RTLMP_AREA_WT](#RTLMP_AREA_WT)
Expand Down
2 changes: 1 addition & 1 deletion flow/designs/asap7/minimal/config.mk
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Expand Up @@ -19,5 +19,5 @@ export SKIP_REPORT_METRICS = 1

# Faster build, remove these in your own config.mk
export SKIP_CTS_REPAIR_TIMING = 1
export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0
export SKIP_INCREMENTAL_REPAIR = 1
2 changes: 1 addition & 1 deletion flow/designs/gf12/ariane/config.mk
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Expand Up @@ -36,4 +36,4 @@ else
export DESIGN_TYPE = CELL_NODEN
endif

export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0
2 changes: 1 addition & 1 deletion flow/designs/gf12/ariane133/config.mk
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Expand Up @@ -30,4 +30,4 @@ else
export DESIGN_TYPE = CELL_NODEN
endif

export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0
2 changes: 1 addition & 1 deletion flow/designs/gf12/swerv_wrapper/config.mk
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Expand Up @@ -36,4 +36,4 @@ else
export DESIGN_TYPE = CELL_NODEN
endif

export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0
2 changes: 1 addition & 1 deletion flow/designs/ihp-sg13g2/aes/config.mk
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Expand Up @@ -13,4 +13,4 @@ export TNS_END_PERCENT = 100

export USE_FILL = 1

export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0
2 changes: 1 addition & 1 deletion flow/designs/ihp-sg13g2/jpeg/config.mk
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Expand Up @@ -10,5 +10,5 @@ export CORE_UTILIZATION = 55
export PLACE_DENSITY_LB_ADDON = 0.20
export TNS_END_PERCENT = 100

export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0

2 changes: 1 addition & 1 deletion flow/designs/sky130hd/aes/config.mk
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Expand Up @@ -16,7 +16,7 @@ export TNS_END_PERCENT = 100

export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl

export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0

export CTS_CLUSTER_SIZE = 20
export CTS_CLUSTER_DIAMETER = 50
2 changes: 1 addition & 1 deletion flow/designs/sky130hd/ibex/BUILD.bazel
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Expand Up @@ -7,7 +7,7 @@ orfs_flow(
"CORE_UTILIZATION": "45",
"PLACE_DENSITY_LB_ADDON": "0.2",
"TNS_END_PERCENT": "100",
"REMOVE_ABC_BUFFERS": "1",
"FLOORPLAN_BUFFERING": "0",
"SYNTH_HDL_FRONTEND": "slang",
"VERILOG_INCLUDE_DIRS": "flow/designs/src/ibex_sv/vendor/lowrisc_ip/prim/rtl",
},
Expand Down
2 changes: 1 addition & 1 deletion flow/designs/sky130hd/ibex/config.mk
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Expand Up @@ -21,7 +21,7 @@ export TNS_END_PERCENT = 100

export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl

export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0

export CTS_CLUSTER_SIZE = 20
export CTS_CLUSTER_DIAMETER = 50
2 changes: 1 addition & 1 deletion flow/designs/sky130hd/jpeg/config.mk
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Expand Up @@ -12,4 +12,4 @@ export TNS_END_PERCENT = 100

export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl

export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0
2 changes: 1 addition & 1 deletion flow/designs/sky130hd/riscv32i/config.mk
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Expand Up @@ -8,4 +8,4 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.
export CORE_UTILIZATION = 45
export PLACE_DENSITY_LB_ADDON = 0.2

export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0
2 changes: 1 addition & 1 deletion flow/designs/sky130hs/aes/config.mk
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Expand Up @@ -12,7 +12,7 @@ export CORE_MARGIN = 2
export PLACE_DENSITY_LB_ADDON = 0.25
export TNS_END_PERCENT = 100

export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0

export CTS_CLUSTER_SIZE = 10
export CTS_CLUSTER_DIAMETER = 50
Expand Down
2 changes: 1 addition & 1 deletion flow/designs/sky130hs/ibex/config.mk
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Expand Up @@ -16,4 +16,4 @@ export CORE_UTILIZATION = 45
export PLACE_DENSITY_LB_ADDON = 0.2
export TNS_END_PERCENT = 100

export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0
2 changes: 1 addition & 1 deletion flow/designs/sky130hs/riscv32i/config.mk
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Expand Up @@ -13,4 +13,4 @@ export TNS_END_PERCENT = 100

export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl

export REMOVE_ABC_BUFFERS = 1
export FLOORPLAN_BUFFERING = 0
5 changes: 0 additions & 5 deletions flow/scripts/abc_speed.script
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Expand Up @@ -28,8 +28,3 @@
&synch2
&nf
&put
buffer -c
topo
stime -c
upsize -c
dnsize -c
27 changes: 20 additions & 7 deletions flow/scripts/floorplan.tcl
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Expand Up @@ -40,6 +40,26 @@ check_setup
set num_instances [llength [get_cells -hier *]]
puts "number instances in verilog is $num_instances"

# Strip all incoming buffers
remove_buffers

set_dont_use $::env(DONT_USE_CELLS)

# Do not buffer chip-level designs
# by default, IO ports will be buffered
# to not buffer IO ports, set environment variable
# DONT_BUFFER_PORT = 1
if { ![env_var_exists_and_non_empty FOOTPRINT] } {
if { ![env_var_equals DONT_BUFFER_PORTS 1] } {
puts "Perform port buffering..."
buffer_ports
}
}

if {[env_var_equals FLOORPLAN_BUFFERING 1]} {
repair_design_helper -pre_placement
}

set additional_args ""
append_env_var additional_args ADDITIONAL_SITES -additional_sites 1

Expand Down Expand Up @@ -103,13 +123,6 @@ if {[env_var_exists_and_non_empty FOOTPRINT_TCL]} {
log_cmd source $::env(FOOTPRINT_TCL)
}

if { [env_var_equals REMOVE_ABC_BUFFERS 1] } {
# remove buffers inserted by yosys/abc
remove_buffers
} else {
repair_timing_helper 0
}

##### Restructure for timing #########
if { [env_var_equals RESYNTH_TIMING_RECOVER 1] } {
repair_design_helper
Expand Down
11 changes: 0 additions & 11 deletions flow/scripts/resize.tcl
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Expand Up @@ -10,17 +10,6 @@ set pin_count_before [sta::network_leaf_pin_count]

set_dont_use $::env(DONT_USE_CELLS)

# Do not buffer chip-level designs
# by default, IO ports will be buffered
# to not buffer IO ports, set environment variable
# DONT_BUFFER_PORT = 1
if { ![env_var_exists_and_non_empty FOOTPRINT] } {
if { ![env_var_equals DONT_BUFFER_PORTS 1] } {
puts "Perform port buffering..."
buffer_ports
}
}

repair_design_helper

if { [env_var_exists_and_non_empty TIE_SEPARATION] } {
Expand Down
12 changes: 6 additions & 6 deletions flow/scripts/util.tcl
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Expand Up @@ -40,14 +40,14 @@ proc repair_timing_helper { {hold_margin 1} } {
log_cmd repair_timing {*}$additional_args
}

proc repair_design_helper {} {
proc repair_design_helper { {extra_args ""} } {
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Just a heads up, used in global_route.tcl too. Should be fine near as I can see.

$ grep -r repair_design_helper scripts/*
scripts/floorplan.tcl:  repair_design_helper
scripts/floorplan.tcl:  repair_design_helper
scripts/global_route.tcl:    repair_design_helper
scripts/resize.tcl:repair_design_helper
scripts/util.tcl:proc repair_design_helper {} {

puts "Perform buffer insertion and gate resizing..."

set additional_args "-verbose"
append_env_var additional_args CAP_MARGIN -cap_margin 1
append_env_var additional_args SLEW_MARGIN -slew_margin 1
append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
log_cmd repair_design {*}$additional_args
set args "-verbose"
append_env_var args CAP_MARGIN -cap_margin 1
append_env_var args SLEW_MARGIN -slew_margin 1
append_env_var args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
log_cmd repair_design {*}$args {*}$extra_args
}

proc recover_power_helper {} {
Expand Down
8 changes: 3 additions & 5 deletions flow/scripts/variables.yaml
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Expand Up @@ -261,14 +261,12 @@ FLOORPLAN_DEF:
stages:
- floorplan
- place
REMOVE_ABC_BUFFERS:
FLOORPLAN_BUFFERING:
description: >
Remove abc buffers from the netlist. If timing repair in floorplanning is
taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early
instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.
Perform a pre-placement buffering round at the floorplan stage.
stages:
- floorplan
deprecated: 1
default: 1
PLACE_SITE:
description: |
Placement site for core cells defined in the technology LEF file.
Expand Down