Update tb.v

test/tb.v

@@ -1,38 +1,33 @@
 `default_nettype none
 `timescale 1ns / 1ps
 
-/* This testbench just instantiates the module and makes some convenient wires
-   that can be driven / tested by the cocotb test.py.
-*/
 module tb ();
 
-  // Dump the signals to a VCD file. You can view it with gtkwave or surfer.
+  // Dump the signals to a VCD file
   initial begin
     $dumpfile("tb.vcd");
     $dumpvars(0, tb);
     #1;
   end
 
-  // Wire up the inputs and outputs:
+  // Clock and reset signals
   reg clk;
   reg rst_n;
   reg ena;
-  reg [7:0] ui_in;
-  reg [7:0] uio_in;
-  wire [7:0] uo_out;
+
+  // Inputs and outputs adapted for TinyTapeout
+  reg [7:0] ui_in;  // Mapped to 'a' (lower 8 bits) and 'b' (upper 8 bits)
+  reg [7:0] uio_in; // Mapped to PB (2 bits)
+  wire [7:0] uo_out; // ALU results
   wire [7:0] uio_out;
   wire [7:0] uio_oe;
 
-  // Replace tt_um_example with your module name:
-  tt_um_example user_project (
-      .ui_in  (ui_in),    // Dedicated inputs
-      .uo_out (uo_out),   // Dedicated outputs
-      .uio_in (uio_in),   // IOs: Input path
-      .uio_out(uio_out),  // IOs: Output path
-      .uio_oe (uio_oe),   // IOs: Enable path (active high: 0=input, 1=output)
-      .ena    (ena),      // enable - goes high when design is selected
-      .clk    (clk),      // clock
-      .rst_n  (rst_n)     // not reset
+  // Instantiating the ALU module
+  tt_um_alu_8bit_JorgeArias8644 user_project (
+      .a      (ui_in[7:0]),  // Map 'a' to lower 8 bits of ui_in
+      .b      (ui_in[15:8]), // Map 'b' to upper 8 bits of ui_in
+      .PB     (uio_in[1:0]), // Map PB to 2 bits of uio_in
+      .led    (uo_out)       // Output mapped to uo_out
   );
 
 endmodule