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Add C perf test code for CPU and FPGA
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‎src_c/cpu_compaction_test.c‎

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#include "stdio.h"
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#include "xtime_l.h"
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#include "data.c"
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#define u32 int
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inline void copy_kv_pairs(u32 *dst, u32 *src, int src_start, int src_end, int dst_start) {
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for (int l = src_start; l < src_end; l++) {
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dst[dst_start++] = src[l];
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}
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}
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int main() {
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// To measure number of clock cycles
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XTime tStart, tEnd;
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const int merged_results_len = merged_len;
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// +1 due to last signal will generate a junk data
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u32 merged_result[merged_results_len + 1];
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// Start testing
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XTime_GetTime(&tStart);
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// Merge two SSTables (file1 and file2)
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int file1Ptr = 0, file2Ptr = 0;
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int mergedPtr = 0;
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int last1 = 0, last2 = 0;
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while (last1 == 0 || last2 == 0) {
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// Get metadata
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u32 meta1 = file1[file1Ptr];
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u32 meta2 = file2[file2Ptr];
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last1 = meta1 & 0x1;
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last2 = meta2 & 0x1;
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u32 key1len = meta1 >> 8 & 0xFF;
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u32 key2len = meta2 >> 8 & 0xFF;
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u32 val1len = meta1 >> 16 & 0xFF;
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u32 val2len = meta2 >> 16 & 0xFF;
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// Compare keys
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int common_key_length = key1len < key2len ? key1len : key2len;
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int winner = 0;
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for (int k = 0; k < common_key_length; k++) {
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if (file1[file1Ptr + 1 + k] < file2[file2Ptr + 1 + k]) {
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// Copy KV pair from file1
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copy_kv_pairs(merged_result, file1, file1Ptr, file1Ptr + key1len + val1len + 1, mergedPtr);
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file1Ptr += key1len + val1len + 1;
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mergedPtr += key1len + val1len + 1;
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winner = 1;
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break;
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} else if (file1[file1Ptr + 1 + k] > file2[file2Ptr + 1 + k]) {
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// Copy KV pair from file2
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copy_kv_pairs(merged_result, file2, file2Ptr, file2Ptr + key2len + val2len + 1, mergedPtr);
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file2Ptr += key2len + val2len + 1;
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mergedPtr += key2len + val2len + 1;
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winner = 1;
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break;
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}
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}
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if (winner == 1) {
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continue;
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}
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// If keys are equal up to a common length, compare key lengths
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if (key1len < key2len) {
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// Copy KV pair from file1
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copy_kv_pairs(merged_result, file1, file1Ptr, file1Ptr + key1len + val1len + 1, mergedPtr);
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file1Ptr += key1len + val1len + 1;
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mergedPtr += key1len + val1len + 1;
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continue;
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} else if (key1len > key2len) {
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// Copy KV pair from file2
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copy_kv_pairs(merged_result, file2, file2Ptr, file2Ptr + key2len + val2len + 1, mergedPtr);
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mergedPtr += key2len + val2len + 1;
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file2Ptr += key2len + val2len + 1;
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continue;
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}
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// If lengths are equal, select file1 cause it is considered more up to date
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copy_kv_pairs(merged_result, file1, file1Ptr, file1Ptr + key1len + val1len + 1, mergedPtr);
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file1Ptr += key1len + val1len + 1;
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mergedPtr += key1len + val1len + 1;
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file2Ptr += key2len + val2len + 1;
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}
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// Copy the rest of the file1 or file2
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if (last1) {
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copy_kv_pairs(merged_result, file2, file2Ptr, file2_len, mergedPtr);
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} else if (last2) {
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copy_kv_pairs(merged_result, file1, file1Ptr, file1_len, mergedPtr);
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}
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// End testing
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XTime_GetTime(&tEnd);
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xil_printf("Processing took %llu clock cycles.\n", 2 * (tEnd - tStart));
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print("Comparing values..\n");
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int errors_num = 0;
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for (int i = 0; i < merged_results_len; i++) {
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if (merged_result[i] != merged[i]) {
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xil_printf("Error at index %d, expected %0x, got %0x\n", i, merged[i], merged_result[i]);
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errors_num++;
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}
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}
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print("Comparing is done. Number of errors is %d\n", errors_num);
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xil_printf("Comparing is done. Number of errors is %d\n", errors_num);
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}
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‎src_c/fpga_compaction_test.c‎

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#include "xaxidma.h"
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#include "xparameters.h"
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#include "xil_cache.h"
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#include "stdio.h"
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#include "xtime_l.h"
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#include "data.c"
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u32 checkHalted(u32 baseAddress, u32 offset);
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u32 init_dma(XAxiDma_Config *dmaConfig, XAxiDma *dma) {
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u32 status = XAxiDma_CfgInitialize(&dma, dmaConfig);
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if(status != XST_SUCCESS){
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print("DMA initialization failed\n");
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return -1;
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}
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print("DMA initialization success..\n");
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return 0;
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}
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int main() {
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// To measure number of clock cycles
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XTime tStart, tEnd;
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const int merged_results_len = merged_len + 1;
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// +1 due to last signal will generate a junk data
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u32 merged_result[merged_results_len + 1];
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u32 status;
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XAxiDma_Config *dma1Config;
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XAxiDma dma1;
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XAxiDma_Config *dma2Config;
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XAxiDma dma2;
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dma1Config = XAxiDma_LookupConfigBaseAddr(XPAR_AXI_DMA_0_BASEADDR);
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dma2Config = XAxiDma_LookupConfigBaseAddr(XPAR_AXI_DMA_1_BASEADDR);
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if (init_dma(dma1Config, &dma1) != 0 || init_dma(dma2Config, &dma2)) {
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return -1;
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}
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status = checkHalted(XPAR_AXI_DMA_0_BASEADDR, 0x4);
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xil_printf("Status for DMA1 before data transfer %0x\n",status);
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status = checkHalted(XPAR_AXI_DMA_1_BASEADDR, 0x4);
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xil_printf("Status for DMA2 before data transfer %0x\n",status);
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// Flush cache for both memory ranges
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Xil_DCacheFlushRange((u32) file1, file1_len*sizeof(u32));
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Xil_DCacheFlushRange((u32) file2, file2_len*sizeof(u32));
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// TODO: set register to start for the LSM-Compactron3000 hardware
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// Start testing
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XTime_GetTime(&tStart);
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// Start DMA transfer to send data to FPGA
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status = XAxiDma_SimpleTransfer(&dma1, (u32) file1, file1_len*sizeof(u32), XAXIDMA_DEVICE_TO_DMA);
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if(status != XST_SUCCESS){
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print("DMA1 transfer failed\n");
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return -1;
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}
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status = XAxiDma_SimpleTransfer(&dma2, (u32) file2, file2_len*sizeof(u32), XAXIDMA_DEVICE_TO_DMA);
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if(status != XST_SUCCESS){
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print("DMA2 transfer failed\n");
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return -1;
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}
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// Start DMA transfer to receive results back
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status = XAxiDma_SimpleTransfer(&dma1, (u32) merged_result, merged_results_len*sizeof(u32), XAXIDMA_DMA_TO_DEVICE);
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if(status != XST_SUCCESS){
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print("DMA1 transfer back failed\n");
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return -1;
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}
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// wait for DMA 1, memory to device to finish
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status = checkHalted(XPAR_AXI_DMA_0_BASEADDR, 0x4);
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while(status != 1) {
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status = checkHalted(XPAR_AXI_DMA_0_BASEADDR, 0x4);
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}
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// wait for DMA 2, memory to device to finish
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status = checkHalted(XPAR_AXI_DMA_1_BASEADDR, 0x4);
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while(status != 1) {
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status = checkHalted(XPAR_AXI_DMA_1_BASEADDR, 0x4);
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}
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// wait for DMA 1, device to memory to finish
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status = checkHalted(XPAR_AXI_DMA_0_BASEADDR, 0x34);
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while(status != 1) {
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status = checkHalted(XPAR_AXI_DMA_0_BASEADDR, 0x34);
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}
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// End testing
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XTime_GetTime(&tEnd);
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print("DMA transfer success..\n");
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xil_printf("Processing took %llu clock cycles.\n", 2 * (tEnd - tStart));
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print("Comparing values..\n");
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int errors_num = 0;
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for (int i=0; i < merged_results_len; i++) {
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if (merged_result[i] != merged[i]) {
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xil_printf("Error at index %d, expected %0x, got %0x\n", i, merged[i], merged_result[i]);
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errors_num++;
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}
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}
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xil_printf("Comparing is done. Number of errors is %d\n", errors_num);
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}
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u32 checkHalted(u32 baseAddress, u32 offset) {
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u32 status = XAxiDma_ReadReg(baseAddress, offset) & XAXIDMA_HALTED_MASK;
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return status;
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}

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