Creating test SSTable files to test end-to-end compaction process

[VMois]

In a Chisel book, to test a custom CPU IP the author used a text file to provide assembly instructions. It would be great before starting developing on real hardware to make sure that our compaction process work correctly. For this, we will need to create a few SSTable files (in a basic text format) with various KV pairs that cover all possible scenarious that can occur during the compaction. This issue covers both creation of test files and creating a full Chisel tests to read files, feed data to circuit, read output and validate it.

It would be really nice if we can run those tests using Verilator backend that is being developed in #21.

The SSTable files created in this issue can be also used for testing after integration with hardware.

[VMois]

It might be beneficial to create a simple binary format for SSTable files as it will make ingestion to custom IP faster. No need to write C/C++ code to convert a text file to binary. This is also the usual way files are stored. I can still create text files but write a short Python script to convert them to binary form.

Binary format should include length of key and value parts, and, of course, key and value data itself.