From 8044182d9b51a3870abbafce51555505a4afe833 Mon Sep 17 00:00:00 2001 From: dzung-hoang Date: Mon, 7 Apr 2025 18:14:30 -0700 Subject: [PATCH] Update rgb2dvi_clocks.xdc Fix "CRITICAL WARNING: [Timing 38-249] Generated clock base_i/video/hdmi_out/frontend/rgb2dvi_0/U0/SerialClk has no logical paths from master clock axi_dynclk_0_PXL_CLK_O." --- boards/ip/rgb2dvi_v1_2/src/rgb2dvi_clocks.xdc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/ip/rgb2dvi_v1_2/src/rgb2dvi_clocks.xdc b/boards/ip/rgb2dvi_v1_2/src/rgb2dvi_clocks.xdc index b5d65a768d..1bedfa6875 100755 --- a/boards/ip/rgb2dvi_v1_2/src/rgb2dvi_clocks.xdc +++ b/boards/ip/rgb2dvi_v1_2/src/rgb2dvi_clocks.xdc @@ -1,2 +1,2 @@ ### Clock constraints ### -create_generated_clock -source [get_ports PixelClk] -multiply_by 5 [get_ports SerialClk] \ No newline at end of file +#create_generated_clock -source [get_ports PixelClk] -multiply_by 5 [get_ports SerialClk]