Commit 1b2405e
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feat: Implement ARM CPU feature detection across Linux, Android, BSD, Windows, macOS, and iOS
**Description:**
This PR replaces the stub `// TODO` implementations in `TArmSimdFeatures` with real, cross-platform ARM hardware capability detection, enabling runtime SIMD dispatch on ARM targets.
### New Units
- **`HlpArmHwCapProvider`** — Platform-abstracted ARM HWCAP provider:
- **Linux/Android:** Resolves `getauxval` via `dlsym` to query `AT_HWCAP`/`AT_HWCAP2`
- **BSD (FreeBSD, NetBSD, DragonFlyBSD):** Resolves `elf_aux_info` / `_elf_aux_info` via `dlsym`
- **Windows ARM64:** Wraps `IsProcessorFeaturePresent` for `PF_ARM_V8_*` constants
- Includes HWCAP bit definitions for both AArch64 and ARM32
- **`HlpDarwinSysCtl`** — Darwin-specific (macOS/iOS) feature detection via `sysctlbyname`, resolved dynamically through `dlsym`. Supports modern `FEAT_*` sysctl keys (macOS 12+) with automatic fallback to legacy keys (macOS 11).
### Changes to Existing Units
- **`HlpArmSimdFeatures`** — All `CPUHas*` methods now contain real detection logic for NEON, AES, SHA1, SHA256, SHA512, SHA3, PMULL, SVE, and SVE2. Added `CPUHasCRC32` / `HasCRC32` for CRC32 instruction detection.
- **`HlpX86SimdFeatures`** — Renamed `FSimdLevel` → `FActiveSimdLevel` and `GetSimdLevel()` → `GetActiveSimdLevel()` for consistency and clarity.
- **`HlpCpuFeatures`** — `TCpuFeatures.X86` and `TCpuFeatures.Arm` properties are now conditionally compiled under `HASHLIB_X86` / `HASHLIB_ARM` respectively, so only the relevant architecture code is included in each build.
- **Include files (`HashLib.inc`, `HashLibFPC.inc`):**
- Renamed `HASHLIB_ARM` (which previously meant ARM32) to `HASHLIB_ARM32` and `HASHLIB_ARM_ASM` to `HASHLIB_ARM32_ASM` to avoid ambiguity
- Introduced `HASHLIB_X86` (= I386 or X86_64) and `HASHLIB_ARM` (= ARM32 or AArch64) as architecture-family defines
- Normalized indentation throughout
- **All dispatch units** (`HlpAdler32Dispatch`, `HlpCRCDispatch`, `HlpBlake2BDispatch`, `HlpBlake2SDispatch`, `HlpBlake3Dispatch`, `HlpSHA1Dispatch`, `HlpSHA2_256Dispatch`, `HlpSHA2_512Dispatch`, `HlpSHA3Dispatch`, `HlpXXHash3Dispatch`, `HlpArgon2Dispatch`, `HlpScryptDispatch`) — Updated to call `GetActiveSimdLevel()` instead of `GetSimdLevel()`.
### Design Notes
- All platform API resolution uses `dlopen(nil)` + `dlsym` at runtime, avoiding hard static imports and gracefully degrading when symbols are unavailable.
- ARM32 vs AArch64 differences in HWCAP register layout (e.g., ARM32 crypto extensions live in `HWCAP2` while AArch64 uses `HWCAP`) are handled via conditional compilation.
- On Windows ARM64, `PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE` bundles AES, PMULL, SHA1, and SHA256 together per Microsoft's documentation. SHA3/SHA512 use the newer `PF_ARM_V82_*` constants.1 parent 87c70b8 commit 1b2405e
24 files changed
Lines changed: 805 additions & 115 deletions
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- HashLib.Benchmark/Delphi
- HashLib.Tests/Delphi.Tests
- HashLib/src
- Checksum
- Crypto
- Hash64
- Include
- KDF
- Packages
- Delphi
- FPC
- Utils
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