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Merge pull request #319 from yrabbit/nextpnr Chipdb builder #925: Commit cbf21d3 pushed by yrabbit
1h 45m 37s master
master
1h 45m 37s
Use nextpnr 0.8 Chipdb builder #924: Pull request #319 opened by yrabbit
1h 45m 55s yrabbit:nextpnr
yrabbit:nextpnr
1h 45m 55s
Build examples using YoWASP Build examples using YoWASP #203: Scheduled
6h 0m 15s master
master
6h 0m 15s
Merge pull request #318 from yrabbit/dlldly Chipdb builder #923: Commit fedeada pushed by pepijndevos
1h 45m 46s 0.17
0.17
1h 45m 46s
Merge pull request #318 from yrabbit/dlldly Chipdb builder #922: Commit fedeada pushed by yrabbit
1h 50m 14s master
master
1h 50m 14s
Implement the DLLDLY primitive. Chipdb builder #921: Pull request #318 synchronize by yrabbit
1h 45m 48s yrabbit:dlldly
yrabbit:dlldly
1h 45m 48s
Implement the DLLDLY primitive. Chipdb builder #920: Pull request #318 synchronize by yrabbit
1h 45m 15s yrabbit:dlldly
yrabbit:dlldly
1h 45m 15s
Merge pull request #314 from yrabbit/seg-clocks Chipdb builder #919: Commit 9e8f061 pushed by yrabbit
1h 44m 57s master
master
1h 44m 57s
Add segmented clock wires. Chipdb builder #918: Pull request #314 synchronize by yrabbit
1h 45m 59s yrabbit:seg-clocks
yrabbit:seg-clocks
1h 45m 59s
Add segmented clock wires. Chipdb builder #917: Pull request #314 synchronize by yrabbit
1h 47m 56s yrabbit:seg-clocks
yrabbit:seg-clocks
1h 47m 56s
Add segmented clock wires. Chipdb builder #916: Pull request #314 synchronize by yrabbit
48m 41s yrabbit:seg-clocks
yrabbit:seg-clocks
48m 41s
Build examples using YoWASP Build examples using YoWASP #202: Scheduled
3h 48m 14s master
master
3h 48m 14s
Merge pull request #317 from yrabbit/pll-hclk Chipdb builder #915: Commit 8401e32 pushed by yrabbit
1h 44m 37s master
master
1h 44m 37s
Merge pull request #316 from yrabbit/clkdiv-clkdiv2 Chipdb builder #914: Commit bf6309b pushed by pepijndevos
1h 47m 12s 0.16
0.16
1h 47m 12s
Implement the DLLDLY primitive. Chipdb builder #913: Pull request #318 opened by yrabbit
26m 26s yrabbit:dlldly
yrabbit:dlldly
26m 26s
Build examples using YoWASP Build examples using YoWASP #201: Scheduled
9m 9s master
master
9m 9s
Add HCLK wires to PLL. Chipdb builder #912: Pull request #317 opened by yrabbit
1h 42m 1s yrabbit:pll-hclk
yrabbit:pll-hclk
1h 42m 1s
Merge pull request #316 from yrabbit/clkdiv-clkdiv2 Chipdb builder #911: Commit bf6309b pushed by yrabbit
1h 43m 40s master
master
1h 43m 40s
Merge pull request #315 from yrabbit/fix-clkdiv-tests Chipdb builder #910: Commit b760177 pushed by yrabbit
1h 40m 29s master
master
1h 40m 29s
Implement CLKDIV2 and CLKDIV for all boards. Chipdb builder #909: Pull request #316 opened by yrabbit
1h 42m 37s yrabbit:clkdiv-clkdiv2
yrabbit:clkdiv-clkdiv2
1h 42m 37s
Build examples using YoWASP Build examples using YoWASP #200: Scheduled
9m 3s master
master
9m 3s
Update tangnano4k.cst Chipdb builder #908: Commit 5148679 pushed by yrabbit
1h 40m 27s master
master
1h 40m 27s
Merge pull request #311 from yrabbit/dff-inputs-0 Chipdb builder #907: Commit ddeb07f pushed by yrabbit
1h 40m 56s master
master
1h 40m 56s
Fix the CLKDIV examples. Chipdb builder #906: Pull request #315 opened by yrabbit
1h 44m 54s yrabbit:fix-clkdiv-tests
yrabbit:fix-clkdiv-tests
1h 44m 54s
Add segmented clock wires. Chipdb builder #905: Pull request #314 opened by yrabbit
1h 40m 0s yrabbit:seg-clocks
yrabbit:seg-clocks
1h 40m 0s
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