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yrabbityrabbit
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PLL in a separate module.
The GW5A series has a different PLL, so we will adapt our examples to future support for the GW5A series. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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12 files changed

+107
-370
lines changed

12 files changed

+107
-370
lines changed

‎examples/DPB.v‎

Lines changed: 6 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -19,46 +19,13 @@ module top
1919
wire key = key_i ^ `INV_BTN;
2020
wire pixel_clk;
2121
wire write_clk;
22-
wire gnd;
23-
assign gnd = 1'b0;
24-
25-
rPLL pll(
26-
.CLKOUT(pixel_clk), // 9MHz
27-
.CLKOUTD(write_clk),
28-
.CLKIN(clk),
29-
.CLKFB(gnd),
30-
.RESET(!rst),
31-
.RESET_P(!rst),
32-
.FBDSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
33-
.IDSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
34-
.ODSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
35-
.DUTYDA({gnd, gnd, gnd, gnd}),
36-
.PSDA({gnd, gnd, gnd, gnd}),
37-
.FDLY({gnd, gnd, gnd, gnd})
38-
);
39-
defparam pll.DEVICE = `PLL_DEVICE;
40-
defparam pll.FCLKIN = `PLL_FCLKIN;
41-
defparam pll.FBDIV_SEL = `PLL_FBDIV_SEL_LCD;
42-
defparam pll.IDIV_SEL = `PLL_IDIV_SEL_LCD;
43-
defparam pll.ODIV_SEL = `PLL_ODIV_SEL;
44-
defparam pll.CLKFB_SEL="internal";
45-
defparam pll.CLKOUTD3_SRC="CLKOUT";
46-
defparam pll.CLKOUTD_BYPASS="false";
47-
defparam pll.CLKOUTD_SRC="CLKOUT";
48-
defparam pll.CLKOUTP_BYPASS="false";
49-
defparam pll.CLKOUTP_DLY_STEP=0;
50-
defparam pll.CLKOUTP_FT_DIR=1'b1;
51-
defparam pll.CLKOUT_BYPASS="false";
52-
defparam pll.CLKOUT_DLY_STEP=0;
53-
defparam pll.CLKOUT_FT_DIR=1'b1;
54-
defparam pll.DUTYDA_SEL="1000";
55-
defparam pll.DYN_DA_EN="false";
56-
defparam pll.DYN_FBDIV_SEL="false";
57-
defparam pll.DYN_IDIV_SEL="false";
58-
defparam pll.DYN_ODIV_SEL="false";
59-
defparam pll.DYN_SDIV_SEL=128;
60-
defparam pll.PSDA_SEL="0000";
6122

23+
clock_pll clok_pll(
24+
.clk(clk),
25+
.rst(rst),
26+
.write_clk(write_clk),
27+
.pixel_clk(pixel_clk));
28+
6229
assign LCD_CLK = pixel_clk;
6330

6431
reg [15:0] pixel_count;

‎examples/DPB16.v‎

Lines changed: 6 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -22,42 +22,12 @@ module top
2222
wire gnd;
2323
assign gnd = 1'b0;
2424

25-
rPLL pll(
26-
.CLKOUT(pixel_clk), // 9MHz
27-
.CLKOUTD(write_clk),
28-
.CLKIN(clk),
29-
.CLKFB(gnd),
30-
.RESET(!rst),
31-
.RESET_P(!rst),
32-
.FBDSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
33-
.IDSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
34-
.ODSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
35-
.DUTYDA({gnd, gnd, gnd, gnd}),
36-
.PSDA({gnd, gnd, gnd, gnd}),
37-
.FDLY({gnd, gnd, gnd, gnd})
38-
);
39-
defparam pll.DEVICE = `PLL_DEVICE;
40-
defparam pll.FCLKIN = `PLL_FCLKIN;
41-
defparam pll.FBDIV_SEL = `PLL_FBDIV_SEL_LCD;
42-
defparam pll.IDIV_SEL = `PLL_IDIV_SEL_LCD;
43-
defparam pll.ODIV_SEL = `PLL_ODIV_SEL;
44-
defparam pll.CLKFB_SEL="internal";
45-
defparam pll.CLKOUTD3_SRC="CLKOUT";
46-
defparam pll.CLKOUTD_BYPASS="false";
47-
defparam pll.CLKOUTD_SRC="CLKOUT";
48-
defparam pll.CLKOUTP_BYPASS="false";
49-
defparam pll.CLKOUTP_DLY_STEP=0;
50-
defparam pll.CLKOUTP_FT_DIR=1'b1;
51-
defparam pll.CLKOUT_BYPASS="false";
52-
defparam pll.CLKOUT_DLY_STEP=0;
53-
defparam pll.CLKOUT_FT_DIR=1'b1;
54-
defparam pll.DUTYDA_SEL="1000";
55-
defparam pll.DYN_DA_EN="false";
56-
defparam pll.DYN_FBDIV_SEL="false";
57-
defparam pll.DYN_IDIV_SEL="false";
58-
defparam pll.DYN_ODIV_SEL="false";
59-
defparam pll.DYN_SDIV_SEL=128;
60-
defparam pll.PSDA_SEL="0000";
25+
26+
clock_pll clok_pll(
27+
.clk(clk),
28+
.rst(rst),
29+
.write_clk(write_clk),
30+
.pixel_clk(pixel_clk));
6131

6232
assign LCD_CLK = pixel_clk;
6333

‎examples/DPX9B.v‎

Lines changed: 5 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -22,42 +22,11 @@ module top
2222
wire gnd;
2323
assign gnd = 1'b0;
2424

25-
rPLL pll(
26-
.CLKOUT(pixel_clk), // 9MHz
27-
.CLKOUTD(write_clk),
28-
.CLKIN(clk),
29-
.CLKFB(gnd),
30-
.RESET(!rst),
31-
.RESET_P(!rst),
32-
.FBDSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
33-
.IDSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
34-
.ODSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
35-
.DUTYDA({gnd, gnd, gnd, gnd}),
36-
.PSDA({gnd, gnd, gnd, gnd}),
37-
.FDLY({gnd, gnd, gnd, gnd})
38-
);
39-
defparam pll.DEVICE = `PLL_DEVICE;
40-
defparam pll.FCLKIN = `PLL_FCLKIN;
41-
defparam pll.FBDIV_SEL = `PLL_FBDIV_SEL_LCD;
42-
defparam pll.IDIV_SEL = `PLL_IDIV_SEL_LCD;
43-
defparam pll.ODIV_SEL = `PLL_ODIV_SEL;
44-
defparam pll.CLKFB_SEL="internal";
45-
defparam pll.CLKOUTD3_SRC="CLKOUT";
46-
defparam pll.CLKOUTD_BYPASS="false";
47-
defparam pll.CLKOUTD_SRC="CLKOUT";
48-
defparam pll.CLKOUTP_BYPASS="false";
49-
defparam pll.CLKOUTP_DLY_STEP=0;
50-
defparam pll.CLKOUTP_FT_DIR=1'b1;
51-
defparam pll.CLKOUT_BYPASS="false";
52-
defparam pll.CLKOUT_DLY_STEP=0;
53-
defparam pll.CLKOUT_FT_DIR=1'b1;
54-
defparam pll.DUTYDA_SEL="1000";
55-
defparam pll.DYN_DA_EN="false";
56-
defparam pll.DYN_FBDIV_SEL="false";
57-
defparam pll.DYN_IDIV_SEL="false";
58-
defparam pll.DYN_ODIV_SEL="false";
59-
defparam pll.DYN_SDIV_SEL=128;
60-
defparam pll.PSDA_SEL="0000";
25+
clock_pll clok_pll(
26+
.clk(clk),
27+
.rst(rst),
28+
.write_clk(write_clk),
29+
.pixel_clk(pixel_clk));
6130

6231
assign LCD_CLK = pixel_clk;
6332

‎examples/DPX9B18.v‎

Lines changed: 6 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -21,42 +21,12 @@ module top
2121
wire gnd;
2222
assign gnd = 1'b0;
2323

24-
rPLL pll(
25-
.CLKOUT(pixel_clk), // 9MHz
26-
.CLKOUTD(write_clk),
27-
.CLKIN(clk),
28-
.CLKFB(gnd),
29-
.RESET(!rst),
30-
.RESET_P(!rst),
31-
.FBDSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
32-
.IDSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
33-
.ODSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
34-
.DUTYDA({gnd, gnd, gnd, gnd}),
35-
.PSDA({gnd, gnd, gnd, gnd}),
36-
.FDLY({gnd, gnd, gnd, gnd})
37-
);
38-
defparam pll.DEVICE = `PLL_DEVICE;
39-
defparam pll.FCLKIN = `PLL_FCLKIN;
40-
defparam pll.FBDIV_SEL = `PLL_FBDIV_SEL_LCD;
41-
defparam pll.IDIV_SEL = `PLL_IDIV_SEL_LCD;
42-
defparam pll.ODIV_SEL = `PLL_ODIV_SEL;
43-
defparam pll.CLKFB_SEL="internal";
44-
defparam pll.CLKOUTD3_SRC="CLKOUT";
45-
defparam pll.CLKOUTD_BYPASS="false";
46-
defparam pll.CLKOUTD_SRC="CLKOUT";
47-
defparam pll.CLKOUTP_BYPASS="false";
48-
defparam pll.CLKOUTP_DLY_STEP=0;
49-
defparam pll.CLKOUTP_FT_DIR=1'b1;
50-
defparam pll.CLKOUT_BYPASS="false";
51-
defparam pll.CLKOUT_DLY_STEP=0;
52-
defparam pll.CLKOUT_FT_DIR=1'b1;
53-
defparam pll.DUTYDA_SEL="1000";
54-
defparam pll.DYN_DA_EN="false";
55-
defparam pll.DYN_FBDIV_SEL="false";
56-
defparam pll.DYN_IDIV_SEL="false";
57-
defparam pll.DYN_ODIV_SEL="false";
58-
defparam pll.DYN_SDIV_SEL=128;
59-
defparam pll.PSDA_SEL="0000";
24+
25+
clock_pll clok_pll(
26+
.clk(clk),
27+
.rst(rst),
28+
.write_clk(write_clk),
29+
.pixel_clk(pixel_clk));
6030

6131
assign LCD_CLK = pixel_clk;
6232

‎examples/Makefile‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -245,7 +245,7 @@ clean:
245245
pll-nanolcd-tangnano20k-synth.json: pll/GW2A-18-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
246246
$(YOSYS) -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@ -family gw2a"
247247

248-
bsram-%-tangnano20k-synth.json: pll/GW2A-18-dyn.vh %-image-rom.v %-video-ram.v %.v
248+
bsram-%-tangnano20k-synth.json: pll/GW2A-18-dyn.vh %-image-rom.v %-video-ram.v %.v clock-rPLL.v
249249
$(YOSYS) -D INV_BTN=1 -p "read_verilog $^; synth_gowin -json $@ -family gw2a"
250250

251251
attosoc-tangnano20k-synth.json: attosoc/attosoc.v attosoc/picorv32.v
@@ -268,7 +268,7 @@ dvi-example-tangnano20k-synth.json: DVI/dvi-example.v DVI/pll480.v DVI/tmds-chan
268268
pll-nanolcd-primer20k-synth.json: pll/GW2A-18-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
269269
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@ -family gw2a"
270270

271-
bsram-%-primer20k-synth.json: pll/GW2A-18-dyn.vh %-image-rom.v %-video-ram.v %.v
271+
bsram-%-primer20k-synth.json: pll/GW2A-18-dyn.vh %-image-rom.v %-video-ram.v %.v clock-rPLL.v
272272
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@ -family gw2a"
273273

274274
attosoc-%-synth.json: attosoc/attosoc.v attosoc/picorv32.v
@@ -291,7 +291,7 @@ dvi-example-primer20k-synth.json: DVI/dvi-example.v DVI/pll480.v DVI/tmds-channe
291291
pll-nanolcd-tangnano-synth.json: pll/GW1N-1-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
292292
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -noalu -json $@"
293293

294-
bsram-%-tangnano-synth.json: pll/GW1N-1-dyn.vh %-image-rom.v %-video-ram.v %.v
294+
bsram-%-tangnano-synth.json: pll/GW1N-1-dyn.vh %-image-rom.v %-video-ram.v %.v clock-rPLL.v
295295
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
296296

297297
# ============================================================
@@ -311,7 +311,7 @@ pll-nanolcd-tangnano1k.fs: pll-nanolcd-tangnano1k.json
311311
pll-nanolcd-tangnano1k-synth.json: pll/GW1NZ-1-dyn.vh pll-nanolcd/TOP.v pll-nanolcd/VGAMod.v
312312
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -noalu -json $@"
313313

314-
bsram-%-tangnano1k-synth.json: pll/GW1NZ-1-dyn.vh %-image-rom.v %-video-ram.v %.v
314+
bsram-%-tangnano1k-synth.json: pll/GW1NZ-1-dyn.vh %-image-rom.v %-video-ram.v %.v clock-rPLL.v
315315
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
316316

317317
# ============================================================
@@ -350,7 +350,7 @@ pll-nanolcd-tangnano9k-synth.json: pll/GW1N-9C-dyn.vh pll-nanolcd/TOP.v pll-nano
350350
pll-nanolcd-tangnano9k.fs: pll-nanolcd-tangnano9k.json
351351
gowin_pack -c -d GW1N-9C --sspi_as_gpio --mspi_as_gpio -o $@ $^
352352

353-
bsram-%-tangnano9k-synth.json: pll/GW1N-9C-dyn.vh %-image-rom.v %-video-ram.v %.v
353+
bsram-%-tangnano9k-synth.json: pll/GW1N-9C-dyn.vh %-image-rom.v %-video-ram.v %.v clock-rPLL.v
354354
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
355355

356356
dvi-example-tangnano9k-synth.json: DVI/dvi-example.v DVI/pll480.v DVI/tmds-channel.v
@@ -370,7 +370,7 @@ dvi-example-tangnano9k-synth.json: DVI/dvi-example.v DVI/pll480.v DVI/tmds-chann
370370
blinky-pll-miniszfpga-synth.json: pll/GW1N-9-dyn.vh blinky-pll.v
371371
$(YOSYS) -D INV_BTN=0 -D LEDS_NR=4 -p "read_verilog $^; synth_gowin -json $@"
372372

373-
bsram-%-miniszfpga-synth.json: pll/GW1N-9-dyn.vh %-image-rom.v %-video-ram.v %.v
373+
bsram-%-miniszfpga-synth.json: pll/GW1N-9-dyn.vh %-image-rom.v %-video-ram.v %.v clock-rPLL.v
374374
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
375375

376376
# ============================================================
@@ -387,7 +387,7 @@ bsram-%-miniszfpga-synth.json: pll/GW1N-9-dyn.vh %-image-rom.v %-video-ram.v %.v
387387
blinky-pll-szfpga-synth.json: pll/GW1N-9-dyn.vh blinky-pll.v
388388
$(YOSYS) -D INV_BTN=0 -D LEDS_NR=4 -p "read_verilog $^; synth_gowin -json $@"
389389

390-
bsram-%-szfpga-synth.json: pll/GW1N-9-dyn.vh %-image-rom.v %-video-ram.v %.v
390+
bsram-%-szfpga-synth.json: pll/GW1N-9-dyn.vh %-image-rom.v %-video-ram.v %.v clock-rPLL.v
391391
$(YOSYS) -D INV_BTN=0 -p "read_verilog $^; synth_gowin -json $@"
392392

393393
# ============================================================

‎examples/SDPB.v‎

Lines changed: 5 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -21,42 +21,11 @@ module top
2121
wire gnd;
2222
assign gnd = 1'b0;
2323

24-
rPLL pll(
25-
.CLKOUT(pixel_clk), // 9MHz
26-
.CLKOUTD(write_clk),
27-
.CLKIN(clk),
28-
.CLKFB(gnd),
29-
.RESET(!rst),
30-
.RESET_P(!rst),
31-
.FBDSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
32-
.IDSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
33-
.ODSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
34-
.DUTYDA({gnd, gnd, gnd, gnd}),
35-
.PSDA({gnd, gnd, gnd, gnd}),
36-
.FDLY({gnd, gnd, gnd, gnd})
37-
);
38-
defparam pll.DEVICE = `PLL_DEVICE;
39-
defparam pll.FCLKIN = `PLL_FCLKIN;
40-
defparam pll.FBDIV_SEL = `PLL_FBDIV_SEL_LCD;
41-
defparam pll.IDIV_SEL = `PLL_IDIV_SEL_LCD;
42-
defparam pll.ODIV_SEL = `PLL_ODIV_SEL;
43-
defparam pll.CLKFB_SEL="internal";
44-
defparam pll.CLKOUTD3_SRC="CLKOUT";
45-
defparam pll.CLKOUTD_BYPASS="false";
46-
defparam pll.CLKOUTD_SRC="CLKOUT";
47-
defparam pll.CLKOUTP_BYPASS="false";
48-
defparam pll.CLKOUTP_DLY_STEP=0;
49-
defparam pll.CLKOUTP_FT_DIR=1'b1;
50-
defparam pll.CLKOUT_BYPASS="false";
51-
defparam pll.CLKOUT_DLY_STEP=0;
52-
defparam pll.CLKOUT_FT_DIR=1'b1;
53-
defparam pll.DUTYDA_SEL="1000";
54-
defparam pll.DYN_DA_EN="false";
55-
defparam pll.DYN_FBDIV_SEL="false";
56-
defparam pll.DYN_IDIV_SEL="false";
57-
defparam pll.DYN_ODIV_SEL="false";
58-
defparam pll.DYN_SDIV_SEL=128;
59-
defparam pll.PSDA_SEL="0000";
24+
clock_pll clok_pll(
25+
.clk(clk),
26+
.rst(rst),
27+
.write_clk(write_clk),
28+
.pixel_clk(pixel_clk));
6029

6130
assign LCD_CLK = pixel_clk;
6231

‎examples/SDPX9B.v‎

Lines changed: 6 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -21,42 +21,12 @@ module top
2121
wire gnd;
2222
assign gnd = 1'b0;
2323

24-
rPLL pll(
25-
.CLKOUT(pixel_clk), // 9MHz
26-
.CLKOUTD(write_clk),
27-
.CLKIN(clk),
28-
.CLKFB(gnd),
29-
.RESET(!rst),
30-
.RESET_P(!rst),
31-
.FBDSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
32-
.IDSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
33-
.ODSEL({gnd, gnd, gnd, gnd, gnd, gnd}),
34-
.DUTYDA({gnd, gnd, gnd, gnd}),
35-
.PSDA({gnd, gnd, gnd, gnd}),
36-
.FDLY({gnd, gnd, gnd, gnd})
37-
);
38-
defparam pll.DEVICE = `PLL_DEVICE;
39-
defparam pll.FCLKIN = `PLL_FCLKIN;
40-
defparam pll.FBDIV_SEL = `PLL_FBDIV_SEL_LCD;
41-
defparam pll.IDIV_SEL = `PLL_IDIV_SEL_LCD;
42-
defparam pll.ODIV_SEL = `PLL_ODIV_SEL;
43-
defparam pll.CLKFB_SEL="internal";
44-
defparam pll.CLKOUTD3_SRC="CLKOUT";
45-
defparam pll.CLKOUTD_BYPASS="false";
46-
defparam pll.CLKOUTD_SRC="CLKOUT";
47-
defparam pll.CLKOUTP_BYPASS="false";
48-
defparam pll.CLKOUTP_DLY_STEP=0;
49-
defparam pll.CLKOUTP_FT_DIR=1'b1;
50-
defparam pll.CLKOUT_BYPASS="false";
51-
defparam pll.CLKOUT_DLY_STEP=0;
52-
defparam pll.CLKOUT_FT_DIR=1'b1;
53-
defparam pll.DUTYDA_SEL="1000";
54-
defparam pll.DYN_DA_EN="false";
55-
defparam pll.DYN_FBDIV_SEL="false";
56-
defparam pll.DYN_IDIV_SEL="false";
57-
defparam pll.DYN_ODIV_SEL="false";
58-
defparam pll.DYN_SDIV_SEL=128;
59-
defparam pll.PSDA_SEL="0000";
24+
clock_pll clok_pll(
25+
.clk(clk),
26+
.rst(rst),
27+
.write_clk(write_clk),
28+
.pixel_clk(pixel_clk));
29+
6030

6131
assign LCD_CLK = pixel_clk;
6232

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