Add a mechanism for fully arbitrary ALUs.

If gowin_pack encounters an ALU with the RAW_ALU_LUT parameter set, the
value of this parameter is used to set the ALU fuse without changes.

This allows, for example, in nextpnr, to disable constant inputs from
networks and modify the ALU LUT so that these inputs do not affect the
result.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

Author: yrabbit

apycula/gowin_pack.py

@@ -2355,16 +2355,30 @@ def place_lut(db, tiledata, tile, parms, num, row, col, slice_attrvals):
 def place_alu(db, tiledata, tile, parms, num, row, col, slice_attrvals):
     lutmap = tiledata.bels[f'LUT{num}'].flags
     alu_bel = tiledata.bels[f"ALU{num}"]
-    mode = str(parms['ALU_MODE'])
     for r_c in lutmap.values():
         for r, c in r_c:
             tile[r][c] = 0
-    if mode in alu_bel.modes:
-        bits = alu_bel.modes[mode]
+    # ALU_RAW_LUT - bits for ALU LUT init value, which are formed in nextpnr as
+    # a result of optimization.
+    if 'RAW_ALU_LUT' in parms:
+        alu_init = parms['RAW_ALU_LUT']
+        if len(alu_init) > 16:
+            alu_init = alu_init[-16:]
+        else:
+            alu_init = alu_init*(16 // len(alu_init))
+        bits = set()
+        for bitnum, bit in enumerate(alu_init[::-1]):
+            if bit == '0':
+                bits.update(lutmap[bitnum])
     else:
-        bits = alu_bel.modes[str(int(mode, 2))]
+        mode = str(parms['ALU_MODE'])
+        if mode in alu_bel.modes:
+            bits = alu_bel.modes[mode]
+        else:
+            bits = alu_bel.modes[str(int(mode, 2))]
     for r, c in bits:
         tile[r][c] = 1
+    #print(row, col, num, bits)
 
     # enable ALU
     alu_mode_attrs = slice_attrvals.setdefault((row, col, int(num) // 2), {})

doc/alu.md

@@ -18,8 +18,8 @@ The ALU hard logic takes the shape of a full adder, where the carry chain is ful
 On the synthesis side, the ALU primitive supports 9 modes, wich correspond to a bit pattern stored in the LUT, as well as which ports are used, and which are set to constant values.
 
 ```
-add(0)    0011000011001100  A:-  B:I0 C:1 D:I1 CIN:0
-sub(1)    1010000001011010  A:I0 B:-  C:1 D:I1 CIN:1
+add(0)    0110000001101010  A:I0 B:I1 C:1 D:-  CIN:0
+sub(1)    1001000010011010  A:I0 B:I1 C:1 D:-  CIN:1
 addsub(2) 0110000010011010  A:I0 B:I1 C:1 D:I3 CIN:??
 ne(3)     1001000010011111  A:I0 B:I1 C:1 D:-  CIN:??
 ge(4)     1001000010011010  A:I0 B:I1 C:1 D:-  CIN:??
@@ -30,12 +30,12 @@ cupcdn(8) 1010000001011010  A:I0 B:I1 C:1 D:I3 CIN:??
 mul(9)    0111100010001000  A:I0 B:I1 C:0 D:1  CIN:??
 ```
 
-These values should be understood as follows: The lowest 4 bits are shared between the `LUT4` in the carry "selector" `LUT2`, so in the case of `ADD` `1100`, selecting `B`. In almost all cases `C:1` which means the output of the `LUT4` is controlled by `AAAA0000AAAA0000` avoiding the lower bits and explainging the zeros in most modes. In the case of `ADD` the `LUT4` function is therefore `00111100`, which is `B XOR D`. In the case of `MUL` `C:0` and `D:1` so indeed only `0000AAAA00000000` is used for the `LUT4`, having the function of `AND`, like the lower `LUT2`. I have confirmed the funcionality is identical with the other clusters set to `0000`. The full list of implemented logic functions:
+These values should be understood as follows: The lowest 4 bits are shared between the `LUT4` in the carry "selector" `LUT2`, so in the case of `ADD` `1010`, selecting `A`. In almost all cases `C:1` which means the output of the `LUT4` is controlled by `AAAA0000AAAA0000` avoiding the lower bits and explainging the zeros in most modes. In the case of `ADD` the `LUT4` function is therefore `01100110`, which is `A XOR B`. In the case of `MUL` `C:0` and `D:1` so indeed only `0000AAAA00000000` is used for the `LUT4`, having the function of `AND`, like the lower `LUT2`. I have confirmed the funcionality is identical with the other clusters set to `0000`. The full list of implemented logic functions:
 
 ```
 FN         LUT4             LUT2
-ADD(0)     B XOR D          B
-SUB(1)     !A XOR D         A
+ADD(0)     A XOR B          A
+SUB(1)     !A XOR B         A
 ADDSUB(2)  A XOR B XOR !D   A
 NE(3)      A XOR B          1
 GE/LE(4-5) A XOR B          A

examples/gw5a/alu-simple.v

@@ -1,6 +1,6 @@
 `default_nettype none
 
 module top(input wire [7:0]a, input wire [7:0]b, output wire [7:0]led);
-	assign led[3:0] = a[3:0] + a[7:4];
+	assign led[3:0] = a[3:0] + {a[7:5], 1'b1};
 endmodule