GW5A. Add OSC (#379)

* GW5A. Add OSC

A programmable on-chip crystal oscillator (OSCA) has been implemented for GW5A-25A.

A distinctive feature of the new series is that the OSC output is no
longer a conventional wire, and therefore routing it through
conventional PIPs is not possible, nor is it possible to "pull" its
signal to the entry point of the global clock wire system.

Nextpnr has been modified to connect the OSC output via an intermediate
clock wire.

In addition, the OSC fuses are also "spread" across the chip like clock
fuses.

* GW5A. OSC divider 3

In addition to even divisors, OSC in the GW5A series also supports
division by 3.

Let's take this into account.

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

Author: yrabbit

apycula/chipdb.py

@@ -461,7 +461,7 @@ def fse_osc(device, fse, ttyp):
     elif device == 'GW1N-2':
         bel = osc.setdefault(f"OSCO", Bel())
     elif device == 'GW5A-25A':
-        bel = osc.setdefault(f"OSCO", Bel())
+        bel = osc.setdefault(f"OSCA", Bel())
     else:
         raise Exception(f"Oscillator not yet supported on {device}")
     bel.portmap = {}
@@ -2247,10 +2247,7 @@ def fse_create_io16(dev, device):
               ('OSC',  'GW1N-9C'):  ({'OSCOUT': 'Q4'}, {}),
               ('OSC',  'GW2A-18'):  ({'OSCOUT': 'Q4'}, {}),
               ('OSC',  'GW2A-18C'):  ({'OSCOUT': 'Q4'}, {}),
-              # XXX unsupported boards, pure theorizing
-              ('OSCO', 'GW1N-2'):  ({'OSCOUT': 'Q7'}, {'OSCEN': (9, 1, 'B4')}),
-              ('OSCW', 'GW2AN-18'):  ({'OSCOUT': 'Q4'}, {}),
-              ('OSCO', 'GW5A-25A'):  ({'OSCOUT': 'Q4'}, {}), # Fix me
+              ('OSCA', 'GW5A-25A'):  ({}, {'OSCOUT': (19, 91, 'OSC_O'), 'OSCEN': (19, 90, 'SEL4')}),
               }
 
 # from logic to global clocks. An interesting piece of dat['CmuxIns'], it was
@@ -2312,15 +2309,39 @@ def fse_create_logic2clk(dev, device, dat: Datfile):
             dev.extra_func.setdefault((row, col), {}).setdefault('clock_gates', []).append(wnames.wirenames[wire_idx])
 
 def fse_create_osc(dev, device, fse):
+    skip_nodes = False
     for row, rd in enumerate(dev.grid):
         for col, rc in enumerate(rd):
             if 51 in fse[rc.ttyp]['shortval']:
+                # None of the supported chips, nor the planned TangMega138k,
+                # have more than one OSC. However, in the GW25 series, the
+                # fuses from Table 51 are found in several cells. The simplest
+                # way to avoid creating duplicate nodes for OSC inputs and
+                # outputs is to create them only in the first cell encountered.
+                if skip_nodes:
+                    dev.extra_func.setdefault((row, col), {}).update({'osc_fuses_only': {}})
+                    continue
                 osc_type = list(fse_osc(device, fse, rc.ttyp).keys())[0]
                 dev.extra_func.setdefault((row, col), {}).update(
                         {'osc': {'type': osc_type}})
                 _, aliases = _osc_ports[osc_type, device]
                 for port, alias in aliases.items():
                     dev.nodes.setdefault(f'X{col}Y{row}/{port}', (port, {(row, col, port)}))[1].add(alias)
+                    # Unlike previous series, GW5A has an OSC output as a clock
+                    # wire, which means that, as a clock source output, it should
+                    # be part of the clock MUX spread across the entire chip.
+                    # Unfortunately, this is not the case—during trial
+                    # compilations, a fuse was noticed for clock pip 520->211 and
+                    # then 211->SPINE. This means that the OSC output is not a
+                    # direct input to the clock MUX. So we are looking for all the
+                    # intermediate wires and making them nodes in the hope that one
+                    # of them will be picked up by the clock MUX.
+                    if port == 'OSCOUT' and device in {'GW5A-25A'}:
+                        a_row, a_col, a_wire = alias
+                        for dest, srcs in dev.grid[a_row][a_col].clock_pips.items():
+                            if a_wire in srcs:
+                                add_node(dev, dest, "GLOBAL_CLK", a_row, a_col, dest)
+                skip_nodes = True
 
 def fse_create_gsr(dev, device):
     # Since, in the general case, there are several cells that have a

apycula/gowin_pack.py

@@ -210,7 +210,7 @@ def get_bits(init_data):
 _dsp_cell_types = {'ALU54D', 'MULT36X36', 'MULTALU36X18', 'MULTADDALU18X18', 'MULTALU18X18', 'MULT18X18', 'MULT9X9', 'PADD18', 'PADD9'}
 def get_bels(data):
     later = []
-    belre = re.compile(r"X(\d+)Y(\d+)/(?:GSR|LUT|DFF|IOB|MUX|ALU|ODDR|OSC[ZFHWO]?|BUF[GS]|RAM16SDP4|RAM16SDP2|RAM16SDP1|PLL|IOLOGIC|CLKDIV2|CLKDIV|BSRAM|ALU|MULTALU18X18|MULTALU36X18|MULTADDALU18X18|MULT36X36|MULT18X18|MULT9X9|PADD18|PADD9|BANDGAP|DQCE|DCS|USERFLASH|EMCU|DHCEN|MIPI_OBUF|MIPI_IBUF|DLLDLY|PINCFG)(\w*)")
+    belre = re.compile(r"X(\d+)Y(\d+)/(?:GSR|LUT|DFF|IOB|MUX|ALU|ODDR|OSC[ZFHWOA]?|BUF[GS]|RAM16SDP4|RAM16SDP2|RAM16SDP1|PLL|IOLOGIC|CLKDIV2|CLKDIV|BSRAM|ALU|MULTALU18X18|MULTALU36X18|MULTADDALU18X18|MULT36X36|MULT18X18|MULT9X9|PADD18|PADD9|BANDGAP|DQCE|DCS|USERFLASH|EMCU|DHCEN|MIPI_OBUF|MIPI_IBUF|DLLDLY|PINCFG)(\w*)")
 
     for cellname, cell in data['modules']['top']['cells'].items():
         if cell['type'].startswith('DUMMY_') or cell['type'] in {'OSER16', 'IDES16'} or 'NEXTPNR_BEL' not in cell['attributes']:
@@ -2018,18 +2018,22 @@ def set_osc_attrs(db, typ, params):
         if param == 'FREQ_DIV':
             fdiv = int(val, 2)
             if fdiv % 2 == 1:
-                raise Exception(f"Divisor of {typ} must be even")
+                if fdiv == 3 and device in {'GW5A-25A'}:
+                    fdiv = 0
+                else:
+                    raise Exception(f"Divisor of {typ} must be even")
             osc_attrs['MCLKCIB'] = fdiv
             osc_attrs['MCLKCIB_EN'] = "ENABLE"
-            osc_attrs['NORMAL'] = "ENABLE"
-            if typ not in {'OSC', 'OSCW'}:
-                osc_attrs['USERPOWER_SAVE'] = 'ENABLE'
             continue
         if param == 'REGULATOR_EN':
             reg = int(val, 2)
             if reg == 1:
                 osc_attrs['OSCREG'] = "ENABLE"
             continue
+    if typ not in {'OSCA'}:
+        osc_attrs['NORMAL'] = "ENABLE"
+    if typ not in {'OSC', 'OSCW'}:
+        osc_attrs['USERPOWER_SAVE'] = 'ENABLE'
 
     fin_attrs = set()
     for attr, val in osc_attrs.items():
@@ -2511,7 +2515,7 @@ def place(db, tilemap, bels, cst, args, slice_attrvals):
         elif typ.startswith("BUFG"):
             continue
 
-        elif typ in {'OSC', 'OSCZ', 'OSCF', 'OSCH', 'OSCW', 'OSCO'}:
+        elif typ in {'OSC', 'OSCZ', 'OSCF', 'OSCH', 'OSCW', 'OSCO', 'OSCA'}:
             # XXX turn on (GW1NZ-1)
             if device == 'GW1NZ-1':
                 en_tiledata = db.grid[db.rows - 1][db.cols - 1]
@@ -2526,9 +2530,21 @@ def place(db, tilemap, bels, cst, args, slice_attrvals):
                 tile[r][c] = 0
 
             osc_attrs = set_osc_attrs(db, typ, parms)
-            bits = get_shortval_fuses(db, tiledata.ttyp, osc_attrs, 'OSC')
-            for r, c in bits:
-                tile[r][c] = 1
+            if device in {'GW5A-25A'}:
+                # set the fuses in all cells
+                for row_col, func_desc in db.extra_func.items():
+                    if 'osc' in func_desc or 'osc_fuses_only' in func_desc:
+                        osc_row, osc_col = row_col
+                        osc_tile = tilemap[osc_row, osc_col]
+                        bits = get_shortval_fuses(db, db.grid[osc_row][osc_col].ttyp, osc_attrs, 'OSC')
+                        #print(osc_row, osc_col, osc_attrs)
+                        for r, c in bits:
+                            osc_tile[r][c] = 1
+            else:
+                bits = get_shortval_fuses(db, tiledata.ttyp, osc_attrs, 'OSC')
+                for r, c in bits:
+                    tile[r][c] = 1
+
         elif typ.startswith("DFF"):
             mode = typ.strip('E')
             place_dff(db, tiledata, tile, parms, num, mode, row, col, slice_attrvals)
@@ -2974,7 +2990,7 @@ def is_clock_pip(src, dest):
         if dest not in wnames.clknumbers:
             return False
         if device in {'GW5A-25A'}:
-            return wnames.clknumbers[src] < wnames.clknumbers['UNK212']
+            return src == 'OSC_O' or wnames.clknumbers[src] < wnames.clknumbers['UNK212']
         # XXX for future
         return wnames.clknumbers[src] < wnames.clknumbers['P10A']
 

apycula/wirenames.py

@@ -333,7 +333,9 @@
 
 clknames_5a25a.update({291: "GT00", 292: "GT10"})
 
-clknames_5a25a.update({n: f"UNK{n}" for n in range(501, 570)})
+clknames_5a25a.update({n: f"UNK{n}" for n in range(501, 520)})
+clknames_5a25a[520] = 'OSC_O';
+clknames_5a25a.update({n: f"UNK{n}" for n in range(521, 570)})
 
 # HCLK->clock network
 # Each HCLK can connect to other HCLKs through two MUXes in the clock system.

examples/gw5a/Makefile

@@ -6,7 +6,8 @@ DEBUG = -v --debug
 .DEFAULT_GOAL := all
 all: \
 	in-out-primer25k.fs in-inv-out-primer25k.fs in-or-inv-out-primer25k.fs \
-	lut8-primer25k.fs big-shift-primer25k.fs alu-simple-primer25k.fs lutram-primer25k.fs
+	lut8-primer25k.fs big-shift-primer25k.fs alu-simple-primer25k.fs lutram-primer25k.fs \
+	blinky-osc-primer25k.fs
 
 
 clean: 
@@ -29,5 +30,5 @@ alu-%-primer25k.json: alu-%-primer25k-synth.json alu-%-primer25k.cst
 	$(NEXTPNR) $(DEBUG) --top top --json $< --write $@ --device GW5A-LV25MG121NES --vopt cst=$(basename $@).cst --vopt cpu_as_gpio --vopt sspi_as_gpio
 
 %-primer25k-synth.json: %.v
-	$(YOSYS) -p "read_verilog $^; synth_gowin -json $@ -family gw5a"
+	$(YOSYS) -D INV_BTN=1 -D LEDS_NR=8 -D OSC_TYPE_OSCA -p "read_verilog $^; synth_gowin -json $@ -family gw5a"
 

examples/gw5a/blinky-osc.v

@@ -0,0 +1,55 @@
+module top (
+	input key_i,
+	output [`LEDS_NR-1:0] led
+);
+
+wire clk;
+
+`ifdef OSC_TYPE_OSC
+OSC osc(
+	.OSCOUT(clk)
+);
+defparam osc.FREQ_DIV=32;
+`elsif OSC_TYPE_OSCZ
+OSCZ osc(
+	.OSCEN(1'b1),
+	.OSCOUT(clk)
+);
+defparam osc.FREQ_DIV=32;
+`elsif OSC_TYPE_OSCF
+OSCF osc(
+	.OSCEN(1'b1),
+	.OSCOUT(clk),
+	.OSCOUT30M()
+);
+defparam osc.FREQ_DIV=32;
+`elsif OSC_TYPE_OSCH
+OSCH osc(
+	.OSCOUT(clk)
+);
+defparam osc.FREQ_DIV=32;
+`elsif OSC_TYPE_OSCA
+OSCA osc(
+	.OSCEN(1'b1),
+	.OSCOUT(clk)
+);
+defparam osc.FREQ_DIV=64;
+`endif
+
+wire key = key_i ^ `INV_BTN;
+
+reg [25:0] ctr_q;
+wire [25:0] ctr_d;
+
+// Sequential code (flip-flop)
+always @(posedge clk) begin
+	if (key) begin
+		ctr_q <= ctr_d;
+	end
+end
+
+// Combinational code (boolean logic)
+assign ctr_d = ctr_q + 1'b1;
+assign led = {ctr_q[25:25-(`LEDS_NR - 2)], |ctr_q[25-(`LEDS_NR - 1):25-(`LEDS_NR)] };
+
+endmodule

examples/gw5a/in-or-inv-out.v

@@ -1,6 +1,7 @@
 `default_nettype none
 
-module top(input wire resetn, input wire key, output wire [7:0]led);
+module top(input wire resetn, input wire key_i, output wire [7:0]led);
+	wire key = key_i ^ `INV_BTN;
 	assign led[4] = !(resetn | key);
 endmodule
 

examples/gw5a/lut8.v

@@ -5,7 +5,9 @@ Connect them as shown in the photo: apuicula/doc/fig/tangprimer25-lut-test.jpeg
 `default_nettype none
 
 (* top *)
-module top(input wire resetn, input wire key, input wire [7:0]pmod_keys, output wire [7:0]led);
+module top(input wire resetn, input wire key_i, input wire [7:0]pmod_keys, output wire [7:0]led);
+	wire key = key_i ^ `INV_BTN;
+
 	wire [7:0]w;
 	assign led = {~w[5], ~w[6], ~w[4:3], ~w[1:0], ~w[2], w[7]};
 

examples/gw5a/primer25k.cst

@@ -34,8 +34,8 @@ IO_PORT "pmod_keys[7]" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
 
 IO_LOC "resetn" H10;
 IO_PORT "resetn" IO_TYPE=LVCMOS33 PULL_MODE=DOWN DRIVE=OFF BANK_VCCIO=3.3;
-IO_LOC "key" H11;
-IO_PORT "key" IO_TYPE=LVCMOS33 PULL_MODE=DOWN DRIVE=OFF BANK_VCCIO=3.3;
+IO_LOC "key_i" H11;
+IO_PORT "key_i" IO_TYPE=LVCMOS33 PULL_MODE=DOWN DRIVE=OFF BANK_VCCIO=3.3;
 
 IO_LOC "clk" E2;
 IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=OFF BANK_VCCIO=3.3;