Add segmented clock wires. #314
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Briefly, these wires can be described as connecting directly to the sinks in a rectangle 4 columns wide and at least 10 rows high. The source can be either at the upper end or at the lower end, which is connected by a system of ‘isolation’ of unused ends. These small nets are useful when the global ones are exhausted or they are not suitable for a given type of sink and/or source - these wires are omnivorous. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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The fact that there are no errors during master-master compilation does not allow us to relax - it's just that I try to maintain compatibility of both new bases with old nextpnr and old bases with new nextpnr 😄 So we wait for YosysHQ/nextpnr#1456 😉 |
…arily for this chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Recent changes to nextpnr should resolve the conflict. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Briefly, these wires can be described as connecting directly to the sinks in a rectangle 4 columns wide and at least 10 rows high. The source can be either at the upper end or at the lower end, which is connected by a system of ‘isolation’ of unused ends.
These small nets are useful when the global ones are exhausted or they are not suitable for a given type of sink and/or source - these wires are omnivorous.