Add HCLK wires to PLL. #317
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Adds the ability to use high-speed clock lines (together with CLKDIV2 type frequency dividers operating on them) as signals for the CLKIN and CLKFB inputs of the rPLL and PLLVR primitives (these cover the full range of supported Gowin chips). Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Adds the ability to use high-speed clock lines (together with CLKDIV2 type frequency dividers operating on them) as signals for the CLKIN and CLKFB inputs of the rPLL and PLLVR primitives (these cover the full range of supported Gowin chips).