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@yrabbit yrabbit commented Mar 12, 2025

DLLDLY is the clock delay primitive that adjust the input clock according to the DLLSTEP signal and outputs the delayed clock.

These primitives are associated with clock pins and are "tapped" between the output of this IBUF and the clock networks, leaving the possibility to connect to the original unshifted signal as well, although the latter is not very practical because it is no longer possible to use fast wires.

yrabbit added 2 commits March 12, 2025 12:05
DLLDLY is the clock delay primitive that adjust the input clock
according to the DLLSTEP signal and outputs the delayed clock.

These primitives are associated with clock pins and are "tapped" between
the output of this IBUF and the clock networks, leaving the possibility
to connect to the original unshifted signal as well, although the latter
is not very practical because it is no longer possible to use fast
wires.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
@yrabbit yrabbit marked this pull request as ready for review March 19, 2025 11:05
A segmented router can (and in most cases will) use global clocks 6 and
7 without regard to the presence of DCS.

Temporarily disallow their use.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
@yrabbit yrabbit merged commit fedeada into YosysHQ:master Mar 20, 2025
31 of 42 checks passed
@yrabbit yrabbit deleted the dlldly branch March 20, 2025 10:01
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