Fix PLL parameter generation script

[yrabbit]

And use the latest version of yosys for CI.

fixes #322

[yrabbit]

Now it can find these 6MHz as well as gowin IDE (#322)

rabbit@void ~/src/pll-freqa/src/gowin_rpll% python ~/src/apicula/apycula/gowin_pll.py -i 27 -o 6 -d "GW1N-1 C6/I5"
/**
 * PLL configuration
 *
 * This Verilog module was generated automatically
 * using the gowin-pll tool.
 * Use at your own risk.
 *
 * Target-Device:                GW1N-1 C6/I5
 * Given input frequency:        27.000 MHz
 * Requested output frequency:   6.000 MHz
 * Achieved output frequency:    6.000 MHz
 */

module pll(
        input  clock_in,
        output clock_out,
        output locked
    );

    rPLL #(
        .FCLKIN("27.0"),
        .IDIV_SEL(8), // -> PFD = 3.0 MHz (range: 3-400 MHz)
        .FBDIV_SEL(1), // -> CLKOUT = 6.0 MHz (range: 3.125-450 MHz)
        .ODIV_SEL(80) // -> VCO = 480.0 MHz (range: 400-900 MHz)
    ) pll (.CLKOUTP(), .CLKOUTD(), .CLKOUTD3(), .RESET(1'b0), .RESET_P(1'b0), .CLKFB(1'b0), .FBDSEL(6'b0), .IDSEL(6'b0), .ODSEL(6'b0), .PSDA(4'b0), .DUTYDA(4'b0), .FDLY(4'b0),
        .CLKIN(clock_in), // 27.0 MHz
        .CLKOUT(clock_out), // 6.0 MHz
        .LOCK(locked)
    );

endmodule