Separate wire descriptions #364
Merged
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
The 5A family brings significant changes to the wiring, especially in terms of clocks. For example, previously there were two pins on each side of the chip for connecting external clock sources, but now there are four on each side. Previously, the PLL had one CLKOUT and a couple of derivative outputs, but now there are 7 independent CLKOUTs for each PLL. And there is an unknown number of new HCLK wires.
These new wires do not fit well into the existing tables, so we will try to split them up.
The select_wires(device) call will select which set of tables to continue working with.
At the moment, they are the same.