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@yrabbit yrabbit commented Aug 5, 2025

The 5A family brings significant changes to the wiring, especially in terms of clocks. For example, previously there were two pins on each side of the chip for connecting external clock sources, but now there are four on each side. Previously, the PLL had one CLKOUT and a couple of derivative outputs, but now there are 7 independent CLKOUTs for each PLL. And there is an unknown number of new HCLK wires.

These new wires do not fit well into the existing tables, so we will try to split them up.

The select_wires(device) call will select which set of tables to continue working with.

At the moment, they are the same.

The 5A family brings significant changes to the wiring, especially in
terms of clocks. For example, previously there were two pins on each
side of the chip for connecting external clock sources, but now there
are four on each side. Previously, the PLL had one CLKOUT and a couple
of derivative outputs, but now there are 7 independent CLKOUTs for each
PLL. And there is an unknown number of new HCLK wires.

These new wires do not fit well into the existing tables, so we will try
to split them up.

The select_wires(device) call will select which set of tables to
continue working with.

At the moment, they are the same.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
@yrabbit yrabbit merged commit d61ef7c into YosysHQ:master Aug 7, 2025
12 of 14 checks passed
@yrabbit yrabbit deleted the split-wires branch August 7, 2025 04:52
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