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@yrabbit yrabbit commented Sep 2, 2025

We pass information about gate wires to nextpnr, since it is possible to connect them as sinks to PIPs, where the clock wires themselves act as sources, which can lead to looping.

We pass information about gate wires to nextpnr, since it is possible to
connect them as sinks to PIPs, where the clock wires themselves act as
sources, which can lead to looping.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
@yrabbit yrabbit merged commit 2cbb2c1 into YosysHQ:master Sep 2, 2025
22 of 28 checks passed
@yrabbit yrabbit deleted the clk-gates branch September 2, 2025 07:42
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