diff --git a/apycula/chipdb.py b/apycula/chipdb.py
index c96a83fb..68ac00ec 100644
--- a/apycula/chipdb.py
+++ b/apycula/chipdb.py
@@ -2308,6 +2308,8 @@ def fse_create_logic2clk(dev, device, dat: Datfile):
         if row != -2:
             add_node(dev, wnames.clknames[clkwire_idx], "GLOBAL_CLK", row, col, wnames.wirenames[wire_idx])
             add_buf_bel(dev, row, col, wnames.wirenames[wire_idx])
+            # Make list of the clock gates for nextpnr
+            dev.extra_func.setdefault((row, col), {}).setdefault('clock_gates', []).append(wnames.wirenames[wire_idx])
 
 def fse_create_osc(dev, device, fse):
     for row, rd in enumerate(dev.grid):