From 525418ffe60cd6336e1973d23eefdaa241e434fd Mon Sep 17 00:00:00 2001 From: YRabbit Date: Tue, 2 Sep 2025 14:59:03 +1000 Subject: [PATCH] Send the gate wires to the nextpnr. We pass information about gate wires to nextpnr, since it is possible to connect them as sinks to PIPs, where the clock wires themselves act as sources, which can lead to looping. Signed-off-by: YRabbit --- apycula/chipdb.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/apycula/chipdb.py b/apycula/chipdb.py index c96a83fb..68ac00ec 100644 --- a/apycula/chipdb.py +++ b/apycula/chipdb.py @@ -2308,6 +2308,8 @@ def fse_create_logic2clk(dev, device, dat: Datfile): if row != -2: add_node(dev, wnames.clknames[clkwire_idx], "GLOBAL_CLK", row, col, wnames.wirenames[wire_idx]) add_buf_bel(dev, row, col, wnames.wirenames[wire_idx]) + # Make list of the clock gates for nextpnr + dev.extra_func.setdefault((row, col), {}).setdefault('clock_gates', []).append(wnames.wirenames[wire_idx]) def fse_create_osc(dev, device, fse): for row, rd in enumerate(dev.grid):