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Send the gate wires to the nextpnr. #381

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Merged
merged 1 commit into from
Sep 2, 2025
Merged

Send the gate wires to the nextpnr. #381

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2 changes: 2 additions & 0 deletions apycula/chipdb.py
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Original file line number Diff line number Diff line change
Expand Up @@ -2308,6 +2308,8 @@ def fse_create_logic2clk(dev, device, dat: Datfile):
if row != -2:
add_node(dev, wnames.clknames[clkwire_idx], "GLOBAL_CLK", row, col, wnames.wirenames[wire_idx])
add_buf_bel(dev, row, col, wnames.wirenames[wire_idx])
# Make list of the clock gates for nextpnr
dev.extra_func.setdefault((row, col), {}).setdefault('clock_gates', []).append(wnames.wirenames[wire_idx])

def fse_create_osc(dev, device, fse):
for row, rd in enumerate(dev.grid):
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