GW5A. Implement PLLs. #388
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Support for all six PLLs in the GW5A-25 chip has been added. All seven outputs with individual output frequency settings are supported. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
plaes
reviewed
Sep 17, 2025
apycula/bslib.py
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| slot_size = ba[3] | ||
| #print("Slot size:", slot_size) | ||
| slot_bitmap = [] | ||
| i = 0 |
apycula/chipdb.py
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| # GW5A PLLs do not use the main grid, but are located in so-called slots, so it | ||
| # makes sense to use the extra_func mechanism for their arbitrary placement. | ||
| # Slots (the name is taken from the ceiling) are bit cells of different widths |
There was a problem hiding this comment.
Probably better to use phrase like "name is chosen arbitrarily".
apycula/chipdb.py
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| # There is one interesting catch here: the hardware has one | ||
| # physical wire as a PLL output, which acts as both a logic | ||
| # and clock signal (let's say F0 and MPLL0CLKOUT0). But if | ||
| # we make a Himabechel node out of them, only one wire will |
apycula/gowin_pack.py
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| if attr.startswith('A_DYN_PE') and attr[-3:] == 'SEL': | ||
| pll_attrs[attr] = val | ||
| continue | ||
| if attr.startswith('A_DE') and attr[-3:] == 'EN': |
One PLL is used to generate seven different frequencies. Since it is impossible to obtain less than 6.25 MHz at the output, the result will have to be viewed on a logic analyzer rather than on LEDs. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Support for all six PLLs in the GW5A-25 chip has been added.
All seven outputs with individual output frequency settings are supported.