0.26

What's Changed

• Turn the logicinfo lists to the dictionaries. by @yrabbit in #385
• Fix ALU. by @yrabbit in #386
• Document the slots. by @yrabbit in #387
• Actually show unknown part type. by @yrabbit in #389
• GW5A. Implement PLLs. by @yrabbit in #388
• GW5A. BUGFIX. Bottom IOs. by @yrabbit in #390
• GW5A. Implement DCS by @yrabbit in #391

Full Changelog: 0.25...0.26

0.25

What's Changed

• Send the gate wires to the nextpnr. by @yrabbit in #381
• GW5A. Add OSC by @yrabbit in #379
• yosys-0.57 by @yrabbit in #382
• Add PLL parameter calculation for new chips. by @yrabbit in #383
• Bump nextpnr version to 0.9 by @yrabbit in #384

Full Changelog: 0.24...0.25

0.24

What's Changed

• Add a mechanism for fully arbitrary ALUs. by @yrabbit in #377
• GW5A. Masquerade for memory cells. by @yrabbit in #378

Full Changelog: 0.23...0.24

0.23

What's Changed

• Update chipdb.yml by @pepijndevos in #370
• Fix CI. by @yrabbit in #371
• Fix the central clock MUX check. by @yrabbit in #372
• GW5A. Add CIN MUX attributes. by @yrabbit in #373
• Modification of fuse installation in slice. by @yrabbit in #374
• GW5A. Enable ALU. by @yrabbit in #375
• GW5A. Add ALU and LUTRAM examples. by @yrabbit in #376

Full Changelog: 0.22...0.23

0.22

What's Changed

• Fix README by @yrabbit in #359
• GW5A. Implement simple IO and logic. by @yrabbit in #360
• Add SSTL entries to _vcc_ios dict in gowin_pack by @UnguidedFreedom in #362
• GW5A. Add CPU/SSPI pin mode switching. by @yrabbit in #363
• Separate wire descriptions by @yrabbit in #364
• Bump Yosys version by @yrabbit in #366
• GW5A. Implement routing of clocks. by @yrabbit in #367

New Contributors

• @UnguidedFreedom made their first contribution in #362

Full Changelog: 0.21...0.22

0.21

What's Changed

• Bump Yosys version to 0.54 by @yrabbit in #349
• Add forgotten wires to IO registers by @yrabbit in #350
• Remove the current setting for True LVDS. by @yrabbit in #352
• Put back the wires with partial fuses. by @yrabbit in #351
• Bump the Yosys version. by @yrabbit in #356

Full Changelog: 0.20...0.21

0.20

What's Changed

• BUGFIX. Use correct IDE files. by @yrabbit in #334
• Use unspecified attributes for CLKDIV/CLKDIV2 by @yrabbit in #336
• Remove a non-existent module from setup. by @yrabbit in #338
• Remove ByteString usages by @xtexx in #340
• Remove bitstream templates. by @yrabbit in #339
• Use a special case of the histogram. by @yrabbit in #341
• update dockerfile by @pepijndevos in #343
• automatically push docker image to docker hub by @pepijndevos in #344
• work around license server issues by @pepijndevos in #346
• Add Module for Tracing Signals by @Seyviour in #303
• Remove extra file. by @yrabbit in #347
• Don't compress EMCU examples. by @yrabbit in #348
• New ide 191003 by @yrabbit in #345

New Contributors

• @xtexx made their first contribution in #340

Full Changelog: 0.19...0.20

Technical release

What's Changed

• Bump the yosys version by @yrabbit in #325
• Eanble segments associated with spines 6 and 7. by @yrabbit in #326
• Add BANK_VCCIO attribute processing. by @yrabbit in #327
• Add BSRAM operation check by @yrabbit in #328
• Defining IO parameters in the examples by @yrabbit in #329
• Bump the Yosys version. by @yrabbit in #330
• Timing calculation by @yrabbit in #331
• Add HCLK delays information. by @yrabbit in #333
• Fixed bitstream compression, tested on tangnano 9k hardware by @regymm in #324

New Contributors

• @regymm made their first contribution in #324

Full Changelog: 0.18...0.19

0.18

What's Changed

• Use nextpnr 0.8 by @yrabbit in #319
• Remove legacy chip databases by @yrabbit in #320
• Fix PLL parameter generation script by @yrabbit in #323

Full Changelog: 0.17...0.18

0.17

What's Changed

• Add HCLK wires to PLL. by @yrabbit in #317
• Add segmented clock wires. by @yrabbit in #314
• Implement the DLLDLY primitive. by @yrabbit in #318

Full Changelog: 0.16...0.17