0.17

pepijndevos released this 20 Mar 11:54

· 162 commits to master since this release

fedeada

What's Changed

Add HCLK wires to PLL. by @yrabbit in #317
Add segmented clock wires. by @yrabbit in #314
Implement the DLLDLY primitive. by @yrabbit in #318

Full Changelog: 0.16...0.17

Contributors

yrabbit

Assets 2