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KAUST Accelerated Connected Computing Lab

Repositories of the KAUST Accelerated Connected Computing Lab

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  1. zypr zypr Public

    Code and documentation for the ZyPR project enabling high level design of partially reconfigured systems on AMD/Xilinx Zynq UltraScale+ FPGA SoCs.

    C 5

  2. interfacer interfacer Public

    Python 1

  3. fp-versal-bench fp-versal-bench Public

    FP performance on pipelined AI Engine vs DSP58

    C++

  4. PRNGine PRNGine Public

    Porting PRNGs to AMD Versal AIEs

    C++

  5. mc-option-pricing-aie mc-option-pricing-aie Public

    Monte Carlo based financial option pricer on AMD Versal AI Engines

    C++

  6. mx-systolic-fpga mx-systolic-fpga Public

    MX Systolic Arrays on FPGAs

    SystemVerilog

Repositories

Showing 6 of 6 repositories
  • mx-systolic-fpga Public

    MX Systolic Arrays on FPGAs

    accl-kaust/mx-systolic-fpga’s past year of commit activity
    SystemVerilog 0 MIT 0 0 0 Updated Oct 19, 2025
  • mc-option-pricing-aie Public

    Monte Carlo based financial option pricer on AMD Versal AI Engines

    accl-kaust/mc-option-pricing-aie’s past year of commit activity
    C++ 0 MIT 0 0 0 Updated Jun 11, 2025
  • PRNGine Public

    Porting PRNGs to AMD Versal AIEs

    accl-kaust/PRNGine’s past year of commit activity
    C++ 0 0 0 0 Updated Mar 15, 2025
  • fp-versal-bench Public

    FP performance on pipelined AI Engine vs DSP58

    accl-kaust/fp-versal-bench’s past year of commit activity
    C++ 0 0 0 0 Updated Jan 20, 2025
  • zypr Public

    Code and documentation for the ZyPR project enabling high level design of partially reconfigured systems on AMD/Xilinx Zynq UltraScale+ FPGA SoCs.

    accl-kaust/zypr’s past year of commit activity
    C 5 BSD-3-Clause 0 0 0 Updated Jan 30, 2023
  • interfacer Public
    accl-kaust/interfacer’s past year of commit activity
    Python 1 0 0 0 Updated Jan 30, 2023

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