nmigen => amaranth rename

Author: hansfbaier

gateware/arrow_deca.py

@@ -1,10 +1,10 @@
 import os
 import subprocess
 
-from nmigen import *
-from nmigen.build import *
-from nmigen.vendor.intel import *
-from nmigen_boards.resources import *
+from amaranth                    import *
+from amaranth.build              import *
+from amaranth.vendor.intel       import *
+from amaranth_boards.resources   import *
 
 from luna.gateware.platform.core import LUNAPlatform, NullPin
 

gateware/deca_mandelbrot.py

@@ -4,12 +4,12 @@
 # SPDX-License-Identifier: CERN-OHL-W-2.0
 import os
 
-from nmigen              import *
-from nmigen.lib.fifo     import AsyncFIFO
+from amaranth            import *
+from amaranth.lib.fifo   import AsyncFIFO
 
-from nmigen_library.debug.ila   import StreamILA, ILACoreParameters
-from nmigen_library.stream      import connect_stream_to_fifo, connect_fifo_to_stream
-from nmigen_library.io.max7219  import SerialLEDArray, NumberToSevenSegmentHex
+from amlib.debug.ila     import StreamILA, ILACoreParameters
+from amlib.stream        import connect_stream_to_fifo, connect_fifo_to_stream
+from amlib.io.max7219    import SerialLEDArray, NumberToSevenSegmentHex
 
 from luna                import top_level_cli
 from luna.usb2           import USBDevice, USBStreamInEndpoint, USBStreamOutEndpoint

gateware/fractalmanager.py

@@ -1,9 +1,9 @@
-from nmigen import *
-from nmigen.build      import Platform
-from nmigen.lib.coding import PriorityEncoder
+from amaranth            import *
+from amaranth.build      import Platform
+from amaranth.lib.coding import PriorityEncoder
 
-from nmigen_library.test   import GatewareTestCase, sync_test_case
-from nmigen_library.stream import StreamInterface
+from amlib.test          import GatewareTestCase, sync_test_case
+from amlib.stream        import StreamInterface
 
 from mandelbrot import Mandelbrot
 

gateware/mandelbrot.py

@@ -1,6 +1,6 @@
-from nmigen import *
-from nmigen.build import Platform
-from nmigen_library.test   import GatewareTestCase, sync_test_case
+from amaranth       import *
+from amaranth.build import Platform
+from amlib.test     import GatewareTestCase, sync_test_case
 
 class Mandelbrot(Elaboratable):
     def __init__(self, *, bitwidth=128, fraction_bits=120, test=False):

requirements.txt

@@ -1,6 +1,6 @@
 pyusb
 numpy
 matplotlib
-git+https://github.com/nmigen/nmigen.git
-git+https://github.com/hansfbaier/usb2-highspeed-core.git
-git+https://github.com/hansfbaier/nmigen-library.git
+git+https://github.com/amaranth-lang/amaranth.git
+git+https://github.com/amaranth-community-unofficial/usb2-highspeed-core.git
+git+https://github.com/amaranth-community-unofficial/amlib.git