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timkpainetimkpaine
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Adding alinx ax7325b
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‎amaranth_boards/alinx_ax7325b.py

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import os
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import subprocess
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from amaranth.build import *
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from amaranth.vendor import XilinxPlatform
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from .resources import *
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__all__ = ["AX7325BPlatform"]
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class AX7325BPlatform(XilinxPlatform):
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"""
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https://www.en.alinx.com/Product/FPGA-Development-Boards/Kintex-7/AX7325B.html
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Power Supply Function
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POWER
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+1.0V FPGA core voltage
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+3.3V FPGA Bank0, Bank14, Bank15, QSIP FLASH, Clock Crystal, SD Card, SFP Optical Module
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+1.8V Gigabit Ethernet, HDMI, USB
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+1.5V DDR3, SODIMM, FPGA Bank33, Bank34, Bank35, VADJ(+2.5V) FPGA Bank12, Bank13, FMC
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VREF, VTT (+0.75V) DDR3, SODIMM
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MGTAVCC(+1.0V) FPGA Bank115, Bank116, Bank117, Bank118
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MGTAVTT(+1.2V) FPGA Bank115, Bank116, Bank117, Bank118
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MGT_1.8V (+1.2V) FPGA GTX auxiliary voltage
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"""
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device = "xc7k325t"
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package = "ffg900"
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speed = "2"
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default_clk = "clk"
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resources = [
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Resource("clk", 0, DiffPairs("AE10", "AF10", dir="i"), Clock(200e6), Attrs(IOSTANDARD="LVDS")),
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Resource("clk0", 0, DiffPairs("F20", "E20", dir="i"), Clock(200e6), Attrs(IOSTANDARD="LVDS")),
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Resource("clk_sfp", 0, DiffPairs("G8", "G7", dir="i"), Clock(156e6), Attrs(IOSTANDARD="LVDS")),
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Resource("clk_qsfp", 0, DiffPairs("C8", "C7", dir="i"), Clock(125e6), Attrs(IOSTANDARD="LVDS")),
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*LEDResources(pins="A22 C19 B19 E18", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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DDR3Resource(0,
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rst_n="Y11",
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clk_p="AG10",
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clk_n="AH10",
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clk_en="AD12",
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cs_n="AF11",
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we_n="AD9",
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ras_n="AE9",
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cas_n="AE11",
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a="AB12 AA8 AB9 AC9 AB13 Y10 AA11 AA10 AA13 AD8 AB10 AC10 AJ9",
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ba="AE8 AC12 AC11",
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dqs_p="Y19 AJ18 AH16 AC16 AH7 AG4 AG2 AD2",
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dqs_n="Y18 AK18 AJ16 AC15 AJ7 AG3 AH1 AD1",
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dq="""AD18 AB18 AD17 AB19 AD16 AC19 AE18 AB17
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AG19 AK19 AD19 AJ19 AF18 AH19 AE19 AG18
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AK15 AJ17 AH15 AF15 AG14 AH17 AG15 AK16
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AE15 Y16 AC14 AA15 AA17 AD14 AA16 AB15
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AK6 AJ8 AJ6 AF8 AK4 AK8 AK5 AG7
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AE4 AF1 AE5 AE1 AF6 AE3 AF5 AF2
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AH4 AJ2 AH5 AJ4 AH2 AK1 AH6 AJ1
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AC2 AC5 AD3 AC7 AE6 AD6 AC1 AC4""",
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dm="AA18 AF17 AE16 Y15 AF7 AF3 AJ3 AD4",
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odt="AD11",
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diff_attrs=Attrs(IOSTANDARD="LVDS"),
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attrs=Attrs(IOSTANDARD="LVCMOS15")),
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DDR3Resource("sodimm",
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rst_n="F17",
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clk_p="D17 E19",
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clk_n="D18 D19",
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clk_en="L17 G17",
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cs_n="F22 C21",
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we_n="H21",
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ras_n="G20",
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cas_n="K20",
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a="F21 D21 E21 F18 H17 B17 J19 C17 J18 C16 K19 G18 K18 G22 D16 L18",
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ba="H19 H20 J17",
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dqs_p="L12 J16 C12 D14 F25 B28 C29 G27",
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dqs_n="L13 H16 B12 C14 E25 A28 B29 F27",
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dq="""L15 K14 J14 L11 K15 L16 J13 K16
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J12 J11 H15 G14 H11 H12 G13 G15
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D12 A11 D13 E13 F11 E11 A12 F12
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B13 A13 B15 C15 B14 A15 E15 F15
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A23 D24 E24 E26 E23 B23 D23 G23
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B24 C24 C26 A27 A25 A26 B27 D26
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D27 A30 C30 D29 C27 B30 E29 E28
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F28 F30 H30 G28 H24 G29 H27 H26""",
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dm="K13 H14 D11 E14 F26 C25 D28 G30",
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odt="D22 H22",
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diff_attrs=Attrs(IOSTANDARD="LVDS"),
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attrs=Attrs(IOSTANDARD="LVCMOS15")),
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# TODO QSPI Flash
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# CCLK B10
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# CE_B U19
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# D0 P24
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# D1 R25
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# D2 R20
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# D3 R21
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# *SPIFlashResources(0,
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# cs_n="", clk="", copi="", cipo="", wp_n="", hold_n="",
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# attrs=Attrs(IOSTANDARD="LVCMOS33")
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# ),
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UARTResource(0,
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rx="AJ26", tx="AK26",
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attrs=Attrs(IOSTANDARD="LVCMOS33")
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),
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# TODO: 4x SFP
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# SFP1_TX_P K2
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# SFP1_TX_N K1
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# SFP1_RX_P K6
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# SFP1_RX_P K5
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# SFP1_TX_DIS T28
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# SFP1_LOSS R28
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# SFP2_TX_P J4
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# SFP2_TX_N J3
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# SFP2_RX_P H6
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# SFP2_RX_P H5
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# SFP2_TX_DIS T28
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# SFP2_LOSS T26
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# SFP3_TX_P H2
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# SFP3_TX_N H1
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# SFP3_RX_P G4
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# SFP3_RX_P G3
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# SFP3_TX_DIS U28
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# SFP3_LOSS U27
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# SFP4_TX_P F2
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# SFP4_TX_N F1
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# SFP4_RX_P F6
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# SFP4_RX_P F5
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# SFP4_TX_DIS U25
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# SFP4_LOSS A18
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# TODO: QSFP
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# QSFP1_TX_P D2
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# QSFP1_TX_N D1
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# QSFP2_TX_P B2
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# QSFP2_TX_N B1
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# QSFP3_TX_P C4
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# QSFP3_TX_N C3
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# QSFP4_TX_P A4
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# QSFP4_TX_N A3
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# QSFP1_RX_P E4
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# QSFP1_RX_N E3
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# QSFP2_RX_P B6
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# QSFP2_RX_N B5
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# QSFP3_RX_P D6
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# QSFP3_RX_N D5
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# QSFP4_RX_P A8
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# QSFP4_RX_N A7
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# QSFP_MODSELL R30
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# QSFP_RESETL U30
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# QSFP_MMODPRSL U22
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# QSFP_INTL R24
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# QSFP_LPMODE V26
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# QSFP_SCL A20
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# QSFP_SDA A21
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# TODO: PCIe x8
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# PCIE_RX0_P M6
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# PCIE_RX0_N M5
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# PCIE_RX1_P P6
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# PCIE_RX1_N P5
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# PCIE_RX2_P R4
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# PCIE_RX2_N R3
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# PCIE_RX3_P T6
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# PCIE_RX3_N T5
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# PCIE_RX4_P V6
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# PCIE_RX4_N V5
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# PCIE_RX5_P W4
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# PCIE_RX5_N W3
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# PCIE_RX6_P Y6
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# PCIE_RX6_N Y5
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# PCIE_RX7_P AA4
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# PCIE_RX7_N AA3
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# PCIE_TX0_P L4
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# PCIE_TX0_N L3
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# PCIE_TX1_P M2
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# PCIE_TX1_N M1
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# PCIE_TX2_P N4
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# PCIE_TX2_N N3
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# PCIE_TX3_P P2
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# PCIE_TX3_N P1
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# PCIE_TX4_P T2
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# PCIE_TX4_N T1
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# PCIE_TX5_P U4
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# PCIE_TX5_N U3
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# PCIE_TX6_P V2
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# PCIE_TX6_N V1
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# PCIE_TX7_P Y2
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# PCIE_TX7_N Y1
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# PCIE_PERST B18
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Resource("temperature", 0,
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Subsignal("scl", Pins("P23", dir="i")),
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Subsignal("sda", Pins("N25", dir="i")),
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Attrs(IOSTANDARD="LVCMOS33")
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),
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*SDCardResources(0, clk="AH21", cmd="AJ21", dat0="AJ22", dat1="AJ23",
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dat2="AG20", dat3="AH20", cd="AE20",
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attrs=Attrs(IOSTANDARD="LVCMOS33")),
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# TODO: FMC
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# TODO: J16 Expansion Header
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*ButtonResources(pins="AG27 AG28", attrs=Attrs(IOSTANDARD="LVCMOS33")),
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]
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connectors = []
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def toolchain_program(self, product, name):
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# openfpgaloader
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openfpgaloader = os.environ.get("OPENFPGALOADER", "openFPGALoader")
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with product.extract("{}.bin".format(name)) as fn:
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# TODO: @timkpaine has digilent_hs3 cable
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subprocess.check_call([openfpgaloader, "-c", "digilent_hs3", fn])
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if __name__ == "__main__":
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from .test.blinky import *
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AX7325BPlatform().build(Blinky(), do_program=True)

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