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AndrDragomirbia1708
AndrDragomir
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bia1708
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adrv9026: Add vcu118 support
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
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‎docs/projects/adrv9026/index.rst‎

Lines changed: 140 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,9 @@ Supported carriers
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* -
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- :xilinx:`VCK190`
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- FMCP1
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* -
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- :xilinx:`VCU118`
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- FMCP
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4043
Block design
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-------------------------------------------------------------------------------
@@ -119,18 +122,18 @@ CPU/Memory interconnects addresses
119122
The addresses are dependent on the architecture of the FPGA, having an offset
120123
added to the base address from HDL (see more at :ref:`architecture`).
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122-
==================== =========== ===========
123-
Instance ZynqMP Versal
124-
==================== =========== ===========
125-
axi_adrv9026_tx_jesd 0x84A90000 0xA4A90000
126-
axi_adrv9026_rx_jesd 0x84AA0000 0xA4AA0000
127-
axi_adrv9026_tx_dma 0x9c420000 0xBC420000
128-
axi_adrv9026_rx_dma 0x9c400000 0xBC400000
129-
tx_adrv9026_tpl_core 0x84A04000 0xA4A04000
130-
rx_adrv9026_tpl_core 0x84A00000 0xA4A00000
131-
axi_adrv9026_tx_xcvr 0x84A80000 0xA4A80000
132-
axi_adrv9026_rx_xcvr 0x84A60000 0xA4A60000
133-
==================== =========== ===========
125+
==================== =========== =========== ===========
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Instance ZynqMP Versal Microblaze
127+
==================== =========== =========== ===========
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axi_adrv9026_tx_jesd 0x84A90000 0xA4A90000 0x44A90000
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axi_adrv9026_rx_jesd 0x84AA0000 0xA4AA0000 0x44AA0000
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axi_adrv9026_tx_dma 0x9c420000 0xBC420000 0x7c420000
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axi_adrv9026_rx_dma 0x9c400000 0xBC400000 0x7c400000
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tx_adrv9026_tpl_core 0x84A04000 0xA4A04000 0x44A04000
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rx_adrv9026_tpl_core 0x84A00000 0xA4A00000 0x44A00000
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axi_adrv9026_tx_xcvr 0x84A80000 0xA4A80000 0x44A80000
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axi_adrv9026_rx_xcvr 0x84A60000 0xA4A60000 0x44A60000
136+
==================== =========== =========== ===========
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135138
SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -155,6 +158,8 @@ SPI connections
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GPIOs
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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161+
ZCU102
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 25 20 20 15
160165
:header-rows: 2
@@ -244,6 +249,97 @@ GPIOs
244249
- 50:32
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- 128:110
246251

252+
VCU118
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 25 20 20 15
256+
:header-rows: 2
257+
258+
* - GPIO signal
259+
- Direction
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- HDL GPIO EMIO
261+
- Software GPIO
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* -
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- (from FPGA view)
264+
-
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- Microblaze
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* - ad9528_reset_b
267+
- INOUT
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- 62
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- 62
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* - ad9528_reset_b
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- INOUT
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- 61
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- 61
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* - adrv9026_tx1_enable
275+
- INOUT
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- 60
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- 60
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* - adrv9026_tx2_enable
279+
- INOUT
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- 59
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- 59
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* - adrv9026_tx3_enable
283+
- INOUT
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- 58
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- 58
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* - adrv9026_tx4_enable
287+
- INOUT
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- 57
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- 57
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* - adrv9026_rx1_enable
291+
- INOUT
292+
- 56
293+
- 56
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* - adrv9026_rx2_enable
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- INOUT
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- 55
297+
- 55
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* - adrv9026_rx3_enable
299+
- INOUT
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- 54
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- 54
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* - adrv9026_rx4_enable
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- INOUT
304+
- 53
305+
- 53
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* - adrv9026_test
307+
- INOUT
308+
- 52
309+
- 52
310+
* - adrv9026_reset_b
311+
- INOUT
312+
- 51
313+
- 51
314+
* - adrv9026_gpint1
315+
- INOUT
316+
- 50
317+
- 50
318+
* - adrv9026_gpint2
319+
- INOUT
320+
- 49
321+
- 49
322+
* - adrv9026_orx_ctrl_a
323+
- INOUT
324+
- 48
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- 48
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* - adrv9026_orx_ctrl_b
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- INOUT
328+
- 47
329+
- 47
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* - adrv9026_orx_ctrl_c
331+
- INOUT
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- 46
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- 46
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* - adrv9026_orx_ctrl_d
335+
- INOUT
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- 45
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- 45
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* - adrv9026_gpio[0:18]
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- INOUT
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- 44:26
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- 44:26
342+
247343
Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
249345

@@ -258,6 +354,17 @@ axi_adrv9026_tx_dma 13 108 140
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axi_adrv9026_rx_dma 14 109 141
259355
==================== === ============ =============
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357+
Microblaze
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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==================== === ============
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Instance name HDL Microblaze
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==================== === ============
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axi_adrv9026_tx_jesd 15 15
363+
axi_adrv9026_rx_jesd 14 14
364+
axi_adrv9026_tx_dma 13 13
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axi_adrv9026_rx_dma 12 12
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==================== === ============
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261368
Building the HDL project
262369
-------------------------------------------------------------------------------
263370

@@ -289,27 +396,27 @@ configure this project, depending on the carrier used.
289396

290397
+-------------------+------------------------------------------------------+
291398
| Parameter | Default value of the parameters depending on carrier |
292-
+-------------------+------------------+----------------+------------------+
293-
| | A10SoC | ZCU102 | VCK190 |
294-
+===================+==================+================+==================+
295-
| JESD_MODE | 8B10B | 8B10B | 8B10B |
296-
+-------------------+------------------+----------------+------------------+
297-
| RX_LANE_RATE | 10 | 10 | 10 |
298-
+-------------------+------------------+----------------+------------------+
299-
| TX_LANE_RATE | 10 | 10 | 10 |
300-
+-------------------+------------------+----------------+------------------+
301-
| RX_JESD_M | 8 | 8 | 8 |
302-
+-------------------+------------------+----------------+------------------+
303-
| RX_JESD_L | 4 | 4 | 4 |
304-
+-------------------+------------------+----------------+------------------+
305-
| RX_JESD_S | 1 | 1 | 1 |
306-
+-------------------+------------------+----------------+------------------+
307-
| TX_JESD_M | 8 | 8 | 8 |
308-
+-------------------+------------------+----------------+------------------+
309-
| TX_JESD_L | 4 | 4 | 4 |
310-
+-------------------+------------------+----------------+------------------+
311-
| TX_JESD_S | 1 | 1 | 1 |
312-
+-------------------+------------------+----------------+------------------+
399+
+-------------------+---------------------------+--------------------------+
400+
| | ZCU102/A10SoC/VCK190/VCU118 |
401+
+===================+======================================================+
402+
| JESD_MODE | 8B10B |
403+
+-------------------+------------------------------------------------------+
404+
| RX_LANE_RATE | 10 |
405+
+-------------------+------------------------------------------------------+
406+
| TX_LANE_RATE | 10 |
407+
+-------------------+------------------------------------------------------+
408+
| RX_JESD_M | 8 |
409+
+-------------------+------------------------------------------------------+
410+
| RX_JESD_L | 4 |
411+
+-------------------+------------------------------------------------------+
412+
| RX_JESD_S | 1 |
413+
+-------------------+------------------------------------------------------+
414+
| TX_JESD_M | 8 |
415+
+-------------------+------------------------------------------------------+
416+
| TX_JESD_L | 4 |
417+
+-------------------+------------------------------------------------------+
418+
| TX_JESD_S | 1 |
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+-------------------+------------------------------------------------------+
313420

314421
A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
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‎projects/adrv9026/common/adrv9026_bd.tcl‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
144144
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
145145
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_2D_TRANSFER 0
146146
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES]
147-
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.MAX_BYTES_PER_BURST 256
147+
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.MAX_BYTES_PER_BURST 4096
148148
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
149149
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.FIFO_SIZE 32
150150

@@ -372,8 +372,8 @@ ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9026_tx_dma/m_src_axi
372372

373373
ad_cpu_interrupt ps-10 mb-15 axi_adrv9026_tx_jesd/irq
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ad_cpu_interrupt ps-11 mb-14 axi_adrv9026_rx_jesd/irq
375-
ad_cpu_interrupt ps-13 mb-12 axi_adrv9026_tx_dma/irq
376-
ad_cpu_interrupt ps-14 mb-11 axi_adrv9026_rx_dma/irq
375+
ad_cpu_interrupt ps-13 mb-13 axi_adrv9026_tx_dma/irq
376+
ad_cpu_interrupt ps-14 mb-12 axi_adrv9026_rx_dma/irq
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378378
# Dummy outputs for unused lanes
379379
if {$ADI_PHY_SEL == 1} {

‎projects/adrv9026/vcu118/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
####################################################################################
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## Copyright (c) 2018 - 2024 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
4+
## Auto-generated, do not modify!
5+
####################################################################################
6+
7+
PROJECT_NAME := adrv9026_vcu118
8+
9+
M_DEPS += ../common/adrv9026_bd.tcl
10+
M_DEPS += ../../scripts/adi_pd.tcl
11+
M_DEPS += ../../common/vcu118/vcu118_system_constr.xdc
12+
M_DEPS += ../../common/vcu118/vcu118_system_bd.tcl
13+
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
14+
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
15+
M_DEPS += ../../../library/common/ad_iobuf.v
16+
17+
LIB_DEPS += axi_dmac
18+
LIB_DEPS += axi_sysid
19+
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
20+
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
21+
LIB_DEPS += jesd204/axi_jesd204_rx
22+
LIB_DEPS += jesd204/axi_jesd204_tx
23+
LIB_DEPS += jesd204/jesd204_rx
24+
LIB_DEPS += jesd204/jesd204_tx
25+
LIB_DEPS += sysid_rom
26+
LIB_DEPS += util_dacfifo
27+
LIB_DEPS += util_pack/util_cpack2
28+
LIB_DEPS += util_pack/util_upack2
29+
LIB_DEPS += xilinx/axi_adxcvr
30+
LIB_DEPS += xilinx/util_adxcvr
31+
32+
include ../../scripts/project-xilinx.mk

‎projects/adrv9026/vcu118/system_bd.tcl‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
###############################################################################
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## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
3+
### SPDX short identifier: ADIBSD
4+
###############################################################################
5+
6+
## FIFO depth is 18Mb - 1M samples
7+
set dac_fifo_address_width 17
8+
9+
source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
10+
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
11+
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
12+
13+
set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
14+
15+
#system ID
16+
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
17+
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
18+
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
19+
20+
sysid_gen_sys_init_file
21+
22+
source ../common/adrv9026_bd.tcl

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