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AndrDragomirAndrDragomir
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adrv9026: Initial design
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
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‎projects/adrv9026/Makefile

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###############################################################################
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## Copyright (C) 2018-2024 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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###############################################################################
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include ../scripts/project-toplevel.mk

‎projects/adrv9026/common/adrv9026_bd.tcl

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###############################################################################
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## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# TX parameters
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set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L
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set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M
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set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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# RX parameters
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set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
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set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
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set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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set dac_fifo_name axi_adrv9026_dacfifo
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set dac_data_width [expr 32*$TX_NUM_OF_LANES]
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set dac_dma_data_width 128
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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# adrv9026
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create_bd_port -dir I dac_fifo_bypass
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create_bd_port -dir I core_clk
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# dac peripherals
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ad_ip_instance axi_adxcvr axi_adrv9026_tx_xcvr
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ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.TX_OR_RX_N 1
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ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.SYS_CLK_SEL 3
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ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.OUT_CLK_SEL 3
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adi_axi_jesd204_tx_create axi_adrv9026_tx_jesd $TX_NUM_OF_LANES
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ad_ip_instance util_upack2 util_adrv9026_tx_upack [list \
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NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_tx_create tx_adrv9026_tpl_core $TX_NUM_OF_LANES \
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$TX_NUM_OF_CONVERTERS \
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$TX_SAMPLES_PER_FRAME \
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$TX_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9026_tx_dma
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.MAX_BYTES_PER_BURST 256
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9026_tx_dma CONFIG.FIFO_SIZE 32
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ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
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# adc peripherals
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ad_ip_instance axi_adxcvr axi_adrv9026_rx_xcvr
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ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.TX_OR_RX_N 0
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ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.SYS_CLK_SEL 0
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ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.OUT_CLK_SEL 3
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adi_axi_jesd204_rx_create axi_adrv9026_rx_jesd $RX_NUM_OF_LANES
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ad_ip_instance util_cpack2 util_adrv9026_rx_cpack [list \
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NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_rx_create rx_adrv9026_tpl_core $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9026_rx_dma
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES]
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.MAX_BYTES_PER_BURST 256
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_parameter axi_adrv9026_rx_dma CONFIG.FIFO_SIZE 32
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# common cores
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ad_ip_instance util_adxcvr util_adrv9026_xcvr
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ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_RATE 10
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ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_RATE 10
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ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1
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ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV 4
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ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5
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ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CLK25_DIV 10
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ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_CLK25_DIV 10
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ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_PMA_CFG 0x001E7080
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ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
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ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_FBDIV 40
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ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_REFCLK_DIV 1
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ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6
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ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15
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# xcvr interfaces
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set tx_ref_clk tx_ref_clk_0
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set rx_ref_clk rx_ref_clk_0
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create_bd_port -dir I $tx_ref_clk
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create_bd_port -dir I $rx_ref_clk
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ad_connect $sys_cpu_resetn util_adrv9026_xcvr/up_rstn
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ad_connect $sys_cpu_clk util_adrv9026_xcvr/up_clk
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# Tx
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ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_tx_xcvr axi_adrv9026_tx_jesd {2 3 1 0} core_clk
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ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_0
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ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_0
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ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_4
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ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_4
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# Rx
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ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_xcvr axi_adrv9026_rx_jesd {} core_clk
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for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
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set ch [expr $i]
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ad_xcvrpll $rx_ref_clk util_adrv9026_xcvr/cpll_ref_clk_$ch
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ad_xcvrpll axi_adrv9026_rx_xcvr/up_pll_rst util_adrv9026_xcvr/up_cpll_rst_$ch
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}
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# connections (dac)
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ad_connect core_clk tx_adrv9026_tpl_core/link_clk
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ad_connect axi_adrv9026_tx_jesd/tx_data tx_adrv9026_tpl_core/link
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ad_connect core_clk util_adrv9026_tx_upack/clk
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ad_connect core_clk_rstgen/peripheral_reset util_adrv9026_tx_upack/reset
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for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect tx_adrv9026_tpl_core/dac_enable_$i util_adrv9026_tx_upack/enable_$i
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ad_connect util_adrv9026_tx_upack/fifo_rd_data_$i tx_adrv9026_tpl_core/dac_data_$i
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}
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ad_connect tx_adrv9026_tpl_core/dac_valid_0 util_adrv9026_tx_upack/fifo_rd_en
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ad_connect core_clk axi_adrv9026_dacfifo/dac_clk
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ad_connect core_clk_rstgen/peripheral_reset axi_adrv9026_dacfifo/dac_rst
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ad_connect util_adrv9026_tx_upack/s_axis_valid VCC
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ad_connect util_adrv9026_tx_upack/s_axis_ready axi_adrv9026_dacfifo/dac_valid
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ad_connect util_adrv9026_tx_upack/s_axis_data axi_adrv9026_dacfifo/dac_data
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ad_connect core_clk axi_adrv9026_dacfifo/dma_clk
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ad_connect core_clk_rstgen/peripheral_reset axi_adrv9026_dacfifo/dma_rst
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ad_connect core_clk axi_adrv9026_tx_dma/m_axis_aclk
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ad_connect axi_adrv9026_dacfifo/dma_valid axi_adrv9026_tx_dma/m_axis_valid
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ad_connect axi_adrv9026_dacfifo/dma_data axi_adrv9026_tx_dma/m_axis_data
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ad_connect axi_adrv9026_dacfifo/dma_ready axi_adrv9026_tx_dma/m_axis_ready
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ad_connect axi_adrv9026_dacfifo/dma_xfer_req axi_adrv9026_tx_dma/m_axis_xfer_req
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ad_connect axi_adrv9026_dacfifo/dma_xfer_last axi_adrv9026_tx_dma/m_axis_last
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ad_connect axi_adrv9026_dacfifo/dac_dunf tx_adrv9026_tpl_core/dac_dunf
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ad_connect axi_adrv9026_dacfifo/bypass dac_fifo_bypass
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ad_connect core_clk_rstgen/peripheral_aresetn axi_adrv9026_tx_dma/m_src_axi_aresetn
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# connections (adc)
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ad_connect core_clk rx_adrv9026_tpl_core/link_clk
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ad_connect axi_adrv9026_rx_jesd/rx_sof rx_adrv9026_tpl_core/link_sof
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ad_connect axi_adrv9026_rx_jesd/rx_data_tdata rx_adrv9026_tpl_core/link_data
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ad_connect axi_adrv9026_rx_jesd/rx_data_tvalid rx_adrv9026_tpl_core/link_valid
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ad_connect core_clk util_adrv9026_rx_cpack/clk
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ad_connect core_clk_rstgen/peripheral_reset util_adrv9026_rx_cpack/reset
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for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect rx_adrv9026_tpl_core/adc_enable_$i util_adrv9026_rx_cpack/enable_$i
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ad_connect rx_adrv9026_tpl_core/adc_data_$i util_adrv9026_rx_cpack/fifo_wr_data_$i
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}
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ad_connect $sys_dma_resetn axi_adrv9026_rx_dma/m_dest_axi_aresetn
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ad_connect rx_adrv9026_tpl_core/adc_valid_0 util_adrv9026_rx_cpack/fifo_wr_en
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ad_connect rx_adrv9026_tpl_core/adc_dovf util_adrv9026_rx_cpack/fifo_wr_overflow
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ad_connect core_clk axi_adrv9026_rx_dma/fifo_wr_clk
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ad_connect util_adrv9026_rx_cpack/packed_fifo_wr axi_adrv9026_rx_dma/fifo_wr
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A00000 rx_adrv9026_tpl_core
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ad_cpu_interconnect 0x44A04000 tx_adrv9026_tpl_core
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ad_cpu_interconnect 0x44A80000 axi_adrv9026_tx_xcvr
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ad_cpu_interconnect 0x44A90000 axi_adrv9026_tx_jesd
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ad_cpu_interconnect 0x7c420000 axi_adrv9026_tx_dma
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ad_cpu_interconnect 0x44A60000 axi_adrv9026_rx_xcvr
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ad_cpu_interconnect 0x44AA0000 axi_adrv9026_rx_jesd
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ad_cpu_interconnect 0x7c400000 axi_adrv9026_rx_dma
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# gt uses hp0, and 100MHz clock for both DRP and AXI4
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ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0
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ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9026_rx_xcvr/m_axi
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# interconnect (mem/dac)
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ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9026_rx_dma/m_dest_axi
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ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9026_tx_dma/m_src_axi
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# interrupts
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ad_cpu_interrupt ps-10 mb-15 axi_adrv9026_tx_jesd/irq
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ad_cpu_interrupt ps-11 mb-14 axi_adrv9026_rx_jesd/irq
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ad_cpu_interrupt ps-13 mb-12 axi_adrv9026_tx_dma/irq
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ad_cpu_interrupt ps-14 mb-11 axi_adrv9026_rx_dma/irq

‎projects/adrv9026/common/adrv9026_fmc.txt

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FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
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#adrv9026
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D4 GBTCLK0_M2C_P FPGA_REF_CLK+ ref_clk_p #N/A #N/A
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D5 GBTCLK0_M2C_N FPGA_REF_CLK- ref_clk_n #N/A #N/A
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H4 CLK0_M2C_P FPGA_MMCM_CLK+ core_clk_p LVDS #N/A
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H5 CLK0_M2C_N FPGA_MMCM_CLK- core_clk_n LVDS #N/A
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A2 DP1_M2C_P SERDOUTA- rx_data_p[0] #N/A #N/A
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A3 DP1_M2C_N SERDOUTA+ rx_data_n[0] #N/A #N/A
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C6 DP0_M2C_P SERDOUTB- rx_data_p[1] #N/A #N/A
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C7 DP0_M2C_N SERDOUTB+ rx_data_n[1] #N/A #N/A
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A6 DP2_M2C_P SERDOUTC- rx_data_p[2] #N/A #N/A
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A7 DP2_M2C_N SERDOUTC+ rx_data_n[2] #N/A #N/A
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A10 DP3_M2C_P SERDOUTD- rx_data_p[3] #N/A #N/A
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A11 DP3_M2C_N SERDOUTD+ rx_data_n[3] #N/A #N/A
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A22 DP1_C2M_P SERDINC+ tx_data_p[0] #N/A #N/A
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A23 DP1_C2M_N SERDINC- tx_data_n[0] #N/A #N/A
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C2 DP0_C2M_P SERDIND- tx_data_p[1] #N/A #N/A
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C3 DP0_C2M_N SERDIND+ tx_data_n[1] #N/A #N/A
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A26 DP2_C2M_P SERDINB- tx_data_p[2] #N/A #N/A
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A27 DP2_C2M_N SERDINB+ tx_data_n[2] #N/A #N/A
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A30 DP3_C2M_P SERDINA+ tx_data_p[3] #N/A #N/A
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A31 DP3_C2M_N SERDINA- tx_data_n[3] #N/A #N/A
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G9 LA03_P SYNCIN1- rx_sync_p LVDS #N/A
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G10 LA03_N SYNCIN1+ rx_sync_n LVDS #N/A
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G36 LA33_P SYNCIN3- rx_sync_2_p LVDS #N/A
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G37 LA33_N SYNCIN3+ rx_sync_2_n LVDS #N/A
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G27 LA25_P SYNCIN2- rx_os_sync_p LVDS #N/A
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G28 LA25_N SYNCIN2+ rx_os_sync_n LVDS #N/A
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G6 LA00_CC_P FPGA_SYSREF+ sysref_p LVDS DIFF_TERM TRUE
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G7 LA00_CC_N FPGA_SYSREF- sysref_n LVDS DIFF_TERM TRUE
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H7 LA02_P SYNCOUT1+ tx_sync_p LVDS DIFF_TERM TRUE
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H8 LA02_N SYNCOUT1- tx_sync_n LVDS DIFF_TERM TRUE
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H28 LA24_P SYNCOUT2 tx_sync_1_p LVDS DIFF_TERM TRUE
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H29 LA24_N SYNCOUT2 tx_sync_1_n LVDS DIFF_TERM TRUE
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C26 LA27_P FMC_CLK_RESETB ad9528_reset_b LVCMOS18 #N/A
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C27 LA27_N FMC_SYSREF_REQUEST ad9528_sysref_req LVCMOS18 #N/A
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D11 LA05_P TEST adrv9026_test LVCMOS18 #N/A
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C10 LA06_P ORX_CTRL_A adrv9026_orx_ctrl_a LVCMOS18 #N/A
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C11 LA06_N ORX_CTRL_B adrv9026_orx_ctrl_b LVCMOS18 #N/A
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D26 LA26_P ORX_CTRL_C adrv9026_orx_ctrl_c LVCMOS18 #N/A
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C15 LA10_N ORX_CTRL_D adrv9026_orx_ctrl_d LVCMOS18 #N/A
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D18 LA13_N RX1_ENABLE adrv9026_rx1_enable LVCMOS18 #N/A
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C19 LA14_N RX2_ENABLE adrv9026_rx2_enable LVCMOS18 #N/A
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D24 LA23_N RX3_ENABLE adrv9026_rx3_enable LVCMOS18 #N/A
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D23 LA23_P RX4_ENABLE adrv9026_rx4_enable LVCMOS18 #N/A
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D17 LA13_P TX1_ENABLE adrv9026_tx1_enable LVCMOS18 #N/A
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C18 LA14_P TX2_ENABLE adrv9026_tx2_enable LVCMOS18 #N/A
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D27 LA26_N TX3_ENABLE adrv9026_tx3_enable LVCMOS18 #N/A
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C14 LA10_P TX4_ENABLE adrv9026_tx4_enable LVCMOS18 #N/A
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H11 LA04_N GPINT1 adrv9026_gpint1 LVCMOS18 #N/A
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H31 LA28_P GPINT2 adrv9026_gpint2 LVCMOS18 #N/A
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H10 LA04_P RESETB adrv9026_reset_b LVCMOS18 #N/A
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H19 LA15_P GPIO_0 adrv9026_gpio_00 LVCMOS18 #N/A
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H20 LA15_N GPIO_1 adrv9026_gpio_01 LVCMOS18 #N/A
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G18 LA16_P GPIO_2 adrv9026_gpio_02 LVCMOS18 #N/A
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G19 LA16_N GPIO_3 adrv9026_gpio_03 LVCMOS18 #N/A
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H25 LA21_P GPIO_4 adrv9026_gpio_04 LVCMOS18 #N/A
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H26 LA21_N GPIO_5 adrv9026_gpio_05 LVCMOS18 #N/A
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C22 LA18_CC_P GPIO_6 adrv9026_gpio_06 LVCMOS18 #N/A
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C23 LA18_CC_N GPIO_7 adrv9026_gpio_07 LVCMOS18 #N/A
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G25 LA22_N GPIO_8 adrv9026_gpio_08 LVCMOS18 #N/A
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H22 LA19_P GPIO_9 adrv9026_gpio_09 LVCMOS18 #N/A
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H23 LA19_N GPIO_10 adrv9026_gpio_10 LVCMOS18 #N/A
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G21 LA20_P GPIO_11 adrv9026_gpio_11 LVCMOS18 #N/A
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G22 LA20_N GPIO_12 adrv9026_gpio_12 LVCMOS18 #N/A
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G31 LA29_N GPIO_13 adrv9026_gpio_13 LVCMOS18 #N/A
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G30 LA29_P GPIO_14 adrv9026_gpio_14 LVCMOS18 #N/A
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G24 LA22_P GPIO_15_FMC adrv9026_gpio_15 LVCMOS18 #N/A
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G16 LA12_N GPIO_16 adrv9026_gpio_16 LVCMOS18 #N/A
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G15 LA12_P GPIO_17 adrv9026_gpio_17 LVCMOS18 #N/A
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D12 LA05_N GPIO_18 adrv9026_gpio_18 LVCMOS18 #N/A
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D14 LA09_P SPI_CS0 spi_csn_adrv9026 LVCMOS18 #N/A
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D15 LA09_N SPI_CS1 spi_csn_ad9528 LVCMOS18 #N/A
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H13 LA07_P SPI_CLK spi_clk LVCMOS18 #N/A
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G12 LA08_P SPI_DOUT spi_miso LVCMOS18 #N/A
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H14 LA07_N SPI_DIN spi_mosi LVCMOS18 #N/A

‎projects/adrv9026/zcu102/Makefile

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###############################################################################
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## Copyright (C) 2018-2024 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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###############################################################################
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PROJECT_NAME := adrv9026_zcu102
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M_DEPS += ../common/adrv9026_bd.tcl
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
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M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
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M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
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M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_sysid
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LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
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LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
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LIB_DEPS += jesd204/axi_jesd204_rx
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LIB_DEPS += jesd204/axi_jesd204_tx
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LIB_DEPS += jesd204/jesd204_rx
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LIB_DEPS += jesd204/jesd204_tx
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_dacfifo
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/util_adxcvr
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include ../../scripts/project-xilinx.mk

‎projects/adrv9026/zcu102/system_bd.tcl

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###############################################################################
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## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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## FIFO depth is 18Mb - 1M samples
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set dac_fifo_address_width 17
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## NOTE: With this configuration the #36Kb BRAM utilization is at ~57%
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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set sys_cstring "sys rom custom string placeholder"
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sysid_gen_sys_init_file $sys_cstring;
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source ../common/adrv9026_bd.tcl

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