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AndrDragomirbia1708
AndrDragomir
authored and
bia1708
committed
adrv9026: Remove vck190 support
Vadj incompatibility between the chip (1.8V) and the FPGA (1.5V) Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
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‎docs/projects/adrv9026/index.rst‎

Lines changed: 16 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -33,9 +33,6 @@ Supported carriers
3333
* -
3434
- :xilinx:`ZCU102`
3535
- FMC HPC1
36-
* -
37-
- :xilinx:`VCK190`
38-
- FMCP1
3936
* -
4037
- :xilinx:`VCU118`
4138
- FMCP
@@ -122,18 +119,18 @@ CPU/Memory interconnects addresses
122119
The addresses are dependent on the architecture of the FPGA, having an offset
123120
added to the base address from HDL (see more at :ref:`architecture`).
124121

125-
==================== =========== =========== ===========
126-
Instance ZynqMP Versal Microblaze
127-
==================== =========== =========== ===========
128-
axi_adrv9026_tx_jesd 0x84A90000 0xA4A90000 0x44A90000
129-
axi_adrv9026_rx_jesd 0x84AA0000 0xA4AA0000 0x44AA0000
130-
axi_adrv9026_tx_dma 0x9c420000 0xBC420000 0x7c420000
131-
axi_adrv9026_rx_dma 0x9c400000 0xBC400000 0x7c400000
132-
tx_adrv9026_tpl_core 0x84A04000 0xA4A04000 0x44A04000
133-
rx_adrv9026_tpl_core 0x84A00000 0xA4A00000 0x44A00000
134-
axi_adrv9026_tx_xcvr 0x84A80000 0xA4A80000 0x44A80000
135-
axi_adrv9026_rx_xcvr 0x84A60000 0xA4A60000 0x44A60000
136-
==================== =========== =========== ===========
122+
==================== =============== ===========
123+
Instance Zynq/Microblaze ZynqMP
124+
==================== =============== ===========
125+
rx_adrv9026_tpl_core 0x44A0_0000 0x84A0_0000
126+
tx_adrv9026_tpl_core 0x44A0_4000 0x84A0_4000
127+
axi_adrv9026_rx_xcvr 0x44A6_0000 0x84A6_0000
128+
axi_adrv9026_tx_xcvr 0x44A8_0000 0x84A8_0000
129+
axi_adrv9026_tx_jesd 0x44A9_0000 0x84A9_0000
130+
axi_adrv9026_rx_jesd 0x44AA_0000 0x84AA_0000
131+
axi_adrv9026_rx_dma 0x7C40_0000 0x9C40_0000
132+
axi_adrv9026_tx_dma 0x7C42_0000 0x9C42_0000
133+
==================== =============== ===========
137134

138135
SPI connections
139136
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -176,7 +173,7 @@ ZCU102
176173
- INOUT
177174
- 68
178175
- 146
179-
* - ad9528_reset_b
176+
* - ad9528_sysref_req
180177
- INOUT
181178
- 67
182179
- 145
@@ -350,8 +347,8 @@ Instance name HDL Linux ZynqMP Actual ZynqMP
350347
==================== === ============ =============
351348
axi_adrv9026_tx_jesd 10 106 138
352349
axi_adrv9026_rx_jesd 11 107 139
353-
axi_adrv9026_tx_dma 13 108 140
354-
axi_adrv9026_rx_dma 14 109 141
350+
axi_adrv9026_tx_dma 13 109 141
351+
axi_adrv9026_rx_dma 14 110 142
355352
==================== === ============ =============
356353

357354
Microblaze
@@ -386,9 +383,6 @@ location and run the make command by typing in your command prompt:
386383
user@analog:~$ cd hdl/projects/adrv9026/zcu102
387384
user@analog:~/hdl/projects/adrv9026/zcu102$ make
388385
389-
user@analog:~$ cd hdl/projects/adrv9026/a10soc
390-
user@analog:~/hdl/projects/adrv9026/a10soc$ make
391-
392386
The following dropdowns contain tables with the parameters that can be used to
393387
configure this project, depending on the carrier used.
394388

@@ -397,7 +391,7 @@ configure this project, depending on the carrier used.
397391
+-------------------+------------------------------------------------------+
398392
| Parameter | Default value of the parameters depending on carrier |
399393
+-------------------+---------------------------+--------------------------+
400-
| | ZCU102/A10SoC/VCK190/VCU118 |
394+
| | ZCU102/A10SoC/VCU118 |
401395
+===================+======================================================+
402396
| JESD_MODE | 8B10B |
403397
+-------------------+------------------------------------------------------+

‎projects/adrv9026/common/adrv9026_bd.tcl‎

Lines changed: 56 additions & 203 deletions
Original file line numberDiff line numberDiff line change
@@ -3,18 +3,6 @@
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
if {![info exists ADI_PHY_SEL]} {
7-
set ADI_PHY_SEL 1
8-
}
9-
10-
if {![info exists INTF_CFG]} {
11-
set INTF_CFG RXTX
12-
}
13-
14-
if {![info exists TRANSCEIVER_TYPE]} {
15-
set TRANSCEIVER_TYPE GTY
16-
}
17-
186
set JESD_MODE $ad_project_params(JESD_MODE)
197
set TX_LANE_RATE $ad_project_params(TX_LANE_RATE)
208
set RX_LANE_RATE $ad_project_params(RX_LANE_RATE)
@@ -66,16 +54,14 @@ create_bd_port -dir I dac_fifo_bypass
6654
create_bd_port -dir I core_clk
6755

6856
# dac peripherals
69-
if {$ADI_PHY_SEL == 1} {
70-
71-
ad_ip_instance axi_adxcvr axi_adrv9026_tx_xcvr
72-
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL
73-
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
74-
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.QPLL_ENABLE 1
75-
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.TX_OR_RX_N 1
76-
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.SYS_CLK_SEL 3
77-
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.OUT_CLK_SEL 3
78-
}
57+
58+
ad_ip_instance axi_adxcvr axi_adrv9026_tx_xcvr
59+
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL
60+
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
61+
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.QPLL_ENABLE 1
62+
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.TX_OR_RX_N 1
63+
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.SYS_CLK_SEL 3
64+
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.OUT_CLK_SEL 3
7965

8066
adi_axi_jesd204_tx_create axi_adrv9026_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL
8167

@@ -104,22 +90,16 @@ ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
10490
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.FIFO_SIZE 32
10591

10692
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
107-
if {$ADI_PHY_SEL == 1} {
93+
10894
# adc peripherals
109-
ad_ip_instance axi_adxcvr axi_adrv9026_rx_xcvr
110-
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL
111-
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
112-
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.QPLL_ENABLE 0
113-
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.TX_OR_RX_N 0
114-
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.SYS_CLK_SEL 0
115-
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.OUT_CLK_SEL 3
116-
}
117-
if {$ADI_PHY_SEL == 0} {
118-
# reset generator
119-
ad_ip_instance proc_sys_reset core_clk_rstgen
120-
ad_connect core_clk core_clk_rstgen/slowest_sync_clk
121-
ad_connect $sys_cpu_resetn core_clk_rstgen/ext_reset_in
122-
}
95+
96+
ad_ip_instance axi_adxcvr axi_adrv9026_rx_xcvr
97+
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL
98+
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
99+
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.QPLL_ENABLE 0
100+
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.TX_OR_RX_N 0
101+
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.SYS_CLK_SEL 0
102+
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.OUT_CLK_SEL 3
123103

124104
adi_axi_jesd204_rx_create axi_adrv9026_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL
125105

@@ -157,136 +137,44 @@ create_bd_port -dir I $tx_ref_clk
157137
create_bd_port -dir I $rx_ref_clk
158138

159139
# common cores
160-
if {$ADI_PHY_SEL == 1} {
161-
ad_ip_instance util_adxcvr util_adrv9026_xcvr
162-
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
163-
ad_ip_parameter util_adrv9026_xcvr CONFIG.LINK_MODE $ENCODER_SEL
164-
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE
165-
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE
166-
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_OUT_DIV 1
167-
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
168-
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1
169-
ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV 4
170-
ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5
171-
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CLK25_DIV 10
172-
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_CLK25_DIV 10
173-
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_PMA_CFG 0x001E7080
174-
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
175-
ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_FBDIV 40
176-
ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_REFCLK_DIV 1
177-
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6
178-
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15
179-
} else {
180-
source ../common/versal_transceiver.tcl
181-
182-
set REF_CLK_RATE [ expr { [info exists ad_project_params(REF_CLK_RATE)] \
183-
? $ad_project_params(REF_CLK_RATE) : 245.76 } ]
184-
185-
create_bd_port -dir I gt_reset
186-
create_bd_port -dir O gt_powergood
187-
create_bd_port -dir O rx_resetdone
188-
create_bd_port -dir O tx_resetdone
189-
create_bd_port -dir I gt_reset_rx_pll_and_datapath
190-
create_bd_port -dir I gt_reset_tx_pll_and_datapath
191-
create_bd_port -dir I gt_reset_rx_datapath
192-
create_bd_port -dir I gt_reset_tx_datapath
193-
194-
switch $INTF_CFG {
195-
"RXTX" {
196-
create_versal_phy jesd204_phy_rxtx $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
197-
set rx_phy jesd204_phy_rxtx
198-
set tx_phy jesd204_phy_rxtx
199-
ad_connect $rx_ref_clk ${rx_phy}/GT_REFCLK
200-
ad_connect gt_reset ${rx_phy}/gtreset_in
201-
ad_connect $sys_cpu_clk ${rx_phy}/s_axi_clk
202-
ad_connect $sys_cpu_resetn ${rx_phy}/s_axi_resetn
203-
ad_connect ${rx_phy}/gtpowergood gt_powergood
204-
ad_connect ${rx_phy}/gtreset_rx_datapath gt_reset_rx_datapath
205-
ad_connect ${rx_phy}/gtreset_tx_datapath gt_reset_tx_datapath
206-
ad_connect ${rx_phy}/gtreset_rx_pll_and_datapath gt_reset_rx_pll_and_datapath
207-
ad_connect ${rx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath
208-
ad_connect ${rx_phy}/rx_resetdone rx_resetdone
209-
ad_connect ${tx_phy}/tx_resetdone tx_resetdone
210-
}
211-
"RX" {
212-
create_versal_phy jesd204_phy_rx $JESD_MODE $RX_NUM_OF_LANES $RX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
213-
set rx_phy jesd204_phy_rx
214-
ad_connect $tx_ref_clk ${rx_phy}/GT_REFCLK
215-
ad_connect gt_reset ${rx_phy}/gtreset_in
216-
ad_connect $sys_cpu_clk ${rx_phy}/s_axi_clk
217-
ad_connect $sys_cpu_resetn ${rx_phy}/s_axi_resetn
218-
ad_connect ${rx_phy}/gtpowergood gt_powergood
219-
ad_connect ${rx_phy}/gtreset_rx_datapath gt_reset_rx_datapath
220-
ad_connect ${rx_phy}/gtreset_rx_pll_and_datapath gt_reset_rx_pll_and_datapath
221-
ad_connect ${rx_phy}/rx_resetdone rx_resetdone
222-
}
223-
"TX" {
224-
create_versal_phy jesd204_phy_tx $JESD_MODE $TX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
225-
set tx_phy jesd204_phy_tx
226-
ad_connect $ref_clock ${tx_phy}/GT_REFCLK
227-
ad_connect gt_reset ${tx_phy}/gtreset_in
228-
ad_connect $sys_cpu_clk ${tx_phy}/s_axi_clk
229-
ad_connect $sys_cpu_resetn ${tx_phy}/s_axi_resetn
230-
ad_connect ${tx_phy}/gtpowergood gt_powergood
231-
ad_connect ${tx_phy}/gtreset_tx_datapath gt_reset_tx_datapath
232-
ad_connect ${tx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath
233-
ad_connect ${tx_phy}/tx_resetdone tx_resetdone
234-
}
235-
}
236-
}
237140

238-
if {$ADI_PHY_SEL == 1} {
239-
ad_connect $sys_cpu_resetn util_adrv9026_xcvr/up_rstn
240-
ad_connect $sys_cpu_clk util_adrv9026_xcvr/up_clk
241-
242-
# Tx
243-
ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_tx_xcvr axi_adrv9026_tx_jesd {3 2 0 1} {} core_clk
244-
ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_0
245-
ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_0
246-
ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_4
247-
ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_4
248-
249-
# Rx
250-
ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_xcvr axi_adrv9026_rx_jesd {} {} core_clk
251-
for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
252-
set ch [expr $i]
253-
ad_xcvrpll $rx_ref_clk util_adrv9026_xcvr/cpll_ref_clk_$ch
254-
ad_xcvrpll axi_adrv9026_rx_xcvr/up_pll_rst util_adrv9026_xcvr/up_cpll_rst_$ch
255-
}
256-
} else {
257-
set rx_link_clock ${rx_phy}/rxusrclk_out
258-
# Connect PHY to Link Layer
259-
ad_connect axi_adrv9026_rx_jesd/rx_phy0 ${rx_phy}/rx1
260-
ad_connect axi_adrv9026_rx_jesd/rx_phy1 ${rx_phy}/rx0
261-
ad_connect axi_adrv9026_rx_jesd/rx_phy2 ${rx_phy}/rx2
262-
ad_connect axi_adrv9026_rx_jesd/rx_phy3 ${rx_phy}/rx3
263-
264-
ad_connect $rx_link_clock /axi_adrv9026_rx_jesd/link_clk
265-
ad_connect core_clk /axi_adrv9026_rx_jesd/device_clk
266-
ad_connect axi_adrv9026_rx_jesd/phy_en_char_align ${rx_phy}/en_char_align
267-
268-
create_bd_port -dir I rx_sysref_0
269-
ad_connect axi_adrv9026_rx_jesd/sysref rx_sysref_0
270-
271-
create_bd_port -dir O rx_sync_0
272-
ad_connect rx_sync_0 axi_adrv9026_rx_jesd/sync
273-
274-
set tx_link_clock ${tx_phy}/txusrclk_out
275-
# Connect PHY to Link Layer
276-
ad_connect axi_adrv9026_tx_jesd/tx_phy0 ${tx_phy}/tx3
277-
ad_connect axi_adrv9026_tx_jesd/tx_phy1 ${tx_phy}/tx2
278-
ad_connect axi_adrv9026_tx_jesd/tx_phy2 ${tx_phy}/tx1
279-
ad_connect axi_adrv9026_tx_jesd/tx_phy3 ${tx_phy}/tx0
280-
281-
ad_connect $tx_link_clock /axi_adrv9026_tx_jesd/link_clk
282-
ad_connect core_clk /axi_adrv9026_tx_jesd/device_clk
283-
284-
create_bd_port -dir I tx_sysref_0
285-
ad_connect axi_adrv9026_tx_jesd/sysref tx_sysref_0
286-
287-
create_bd_port -dir I tx_sync_0
288-
ad_connect tx_sync_0 axi_adrv9026_tx_jesd/sync
141+
ad_ip_instance util_adxcvr util_adrv9026_xcvr
142+
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
143+
ad_ip_parameter util_adrv9026_xcvr CONFIG.LINK_MODE $ENCODER_SEL
144+
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE
145+
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE
146+
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_OUT_DIV 1
147+
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
148+
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1
149+
ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV 4
150+
ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5
151+
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CLK25_DIV 10
152+
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_CLK25_DIV 10
153+
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_PMA_CFG 0x001E7080
154+
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
155+
ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_FBDIV 40
156+
ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_REFCLK_DIV 1
157+
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6
158+
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15
159+
160+
ad_connect $sys_cpu_resetn util_adrv9026_xcvr/up_rstn
161+
ad_connect $sys_cpu_clk util_adrv9026_xcvr/up_clk
162+
163+
# Tx
164+
ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_tx_xcvr axi_adrv9026_tx_jesd {3 2 0 1} {} core_clk
165+
ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_0
166+
ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_0
167+
ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_4
168+
ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_4
169+
170+
# Rx
171+
ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_xcvr axi_adrv9026_rx_jesd {} {} core_clk
172+
for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
173+
set ch [expr $i]
174+
ad_xcvrpll $rx_ref_clk util_adrv9026_xcvr/cpll_ref_clk_$ch
175+
ad_xcvrpll axi_adrv9026_rx_xcvr/up_pll_rst util_adrv9026_xcvr/up_cpll_rst_$ch
289176
}
177+
290178
# connections (dac)
291179

292180
ad_connect core_clk tx_adrv9026_tpl_core/link_clk
@@ -345,10 +233,8 @@ ad_connect util_adrv9026_rx_cpack/packed_fifo_wr axi_adrv9026_rx_dma/fifo_wr
345233

346234
ad_cpu_interconnect 0x44A00000 rx_adrv9026_tpl_core
347235
ad_cpu_interconnect 0x44A04000 tx_adrv9026_tpl_core
348-
if {$ADI_PHY_SEL == 1} {
349-
ad_cpu_interconnect 0x44A60000 axi_adrv9026_rx_xcvr
350-
ad_cpu_interconnect 0x44A80000 axi_adrv9026_tx_xcvr
351-
}
236+
ad_cpu_interconnect 0x44A60000 axi_adrv9026_rx_xcvr
237+
ad_cpu_interconnect 0x44A80000 axi_adrv9026_tx_xcvr
352238
ad_cpu_interconnect 0x44A90000 axi_adrv9026_tx_jesd
353239
ad_cpu_interconnect 0x7c420000 axi_adrv9026_tx_dma
354240
ad_cpu_interconnect 0x44AA0000 axi_adrv9026_rx_jesd
@@ -357,9 +243,7 @@ ad_cpu_interconnect 0x7c400000 axi_adrv9026_rx_dma
357243
# gt uses hp0, and 100MHz clock for both DRP and AXI4
358244

359245
ad_mem_hp0_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP0
360-
if {$ADI_PHY_SEL == 1} {
361-
ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9026_rx_xcvr/m_axi
362-
}
246+
ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9026_rx_xcvr/m_axi
363247

364248
# interconnect (mem/dac)
365249

@@ -374,34 +258,3 @@ ad_cpu_interrupt ps-10 mb-15 axi_adrv9026_tx_jesd/irq
374258
ad_cpu_interrupt ps-11 mb-14 axi_adrv9026_rx_jesd/irq
375259
ad_cpu_interrupt ps-13 mb-13 axi_adrv9026_tx_dma/irq
376260
ad_cpu_interrupt ps-14 mb-12 axi_adrv9026_rx_dma/irq
377-
378-
# Dummy outputs for unused lanes
379-
if {$ADI_PHY_SEL == 1} {
380-
if {$INTF_CFG != "TX"} {
381-
# Unused Rx lanes
382-
for {set i $RX_NUM_OF_LANES} {$i < 4} {incr i} {
383-
create_bd_port -dir I rx_data_${i}_n
384-
create_bd_port -dir I rx_data_${i}_p
385-
}
386-
}
387-
if {$INTF_CFG != "RX"} {
388-
# Unused Tx lanes
389-
for {set i $TX_NUM_OF_LANES} {$i < 4} {incr i} {
390-
create_bd_port -dir O tx_data_${i}_n
391-
create_bd_port -dir O tx_data_${i}_p
392-
}
393-
}
394-
} else {
395-
if {$INTF_CFG != "TX"} {
396-
create_bd_port -dir I -from 3 -to 0 rx_0_p
397-
create_bd_port -dir I -from 3 -to 0 rx_0_n
398-
ad_connect rx_0_p ${rx_phy}/rx_0_p
399-
ad_connect rx_0_n ${rx_phy}/rx_0_n
400-
}
401-
if {$INTF_CFG != "RX"} {
402-
create_bd_port -dir O -from 3 -to 0 tx_0_p
403-
create_bd_port -dir O -from 3 -to 0 tx_0_n
404-
ad_connect tx_0_p ${rx_phy}/tx_0_p
405-
ad_connect tx_0_n ${rx_phy}/tx_0_n
406-
}
407-
}

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