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AndreiGrozav
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PR Description

Add build time, selectable, Tx channel interface clock selection.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • [] I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Add info regarding selectable Tx clock source during build time.

Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
#
# e.g.
# make USE_RX_CLK_FOR_TX1=0 USE_RX_CLK_FOR_TX2=0
#
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Even though it might sound redundant, I would add a line with the parameter name and description, before the available value options (for both USE_RX_CLK_FOR_TX1 and USE_RX_CLK_FOR_TX2).
Keep the comments section uninterrupted by tcl commands and "set" the parameters after the comments section.

Here is a good example: https://github.com/analogdevicesinc/hdl/blob/main/projects/ad4630_fmc/zed/system_project.tcl#L15-L20


set CMOS_LVDS_N [get_env_param CMOS_LVDS_N 1]

# 0 = Tx1 SSI reference clock
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Same here, add param name & description before the enumerated possible values.

#
# e.g.
# make USE_RX_CLK_FOR_TX1=0 USE_RX_CLK_FOR_TX2=0
#
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Same here.

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2 participants